360 lines
26 KiB
C
360 lines
26 KiB
C
/**
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******************************************************************************
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* @file mx25lm51245g.h
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* @modify MCD Application Team
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* @brief This file contains all the description of the
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* MX25LM51245G OSPI memory.
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2018 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef MX25LM51245G_H
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#define MX25LM51245G_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "mx25lm51245g_conf.h"
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/** @addtogroup BSP
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* @{
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*/
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/** @addtogroup Components
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* @{
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*/
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/** @addtogroup MX25LM51245G
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* @{
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*/
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/** @defgroup MX25LM51245G_Exported_Constants MX25LM51245G Exported Constants
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* @{
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*/
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/**
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* @brief MX25LM51245G Size configuration
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*/
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#define MX25LM51245G_SECTOR_64K (uint32_t)(64 * 1024) /* 1024 sectors of 64KBytes */
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#define MX25LM51245G_SUBSECTOR_4K (uint32_t)(4 * 1024) /* 16384 subsectors of 4KBytes */
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#define MX25LM51245G_FLASH_SIZE (uint32_t)(512*1024*1024/8) /* 512 Mbits => 64MBytes */
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#define MX25LM51245G_PAGE_SIZE (uint32_t)256 /* 262144 pages of 256 Bytes */
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/**
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* @brief MX25LM51245G Timing configuration
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*/
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#define MX25LM51245G_BULK_ERASE_MAX_TIME 460000U
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#define MX25LM51245G_SECTOR_ERASE_MAX_TIME 1000U
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#define MX25LM51245G_SUBSECTOR_4K_ERASE_MAX_TIME 400U
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#define MX25LM51245G_WRITE_REG_MAX_TIME 40U
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#define MX25LM51245G_RESET_MAX_TIME 100U /* when SWreset during erase operation */
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#define MX25LM51245G_AUTOPOLLING_INTERVAL_TIME 0x10U
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/**
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* @brief MX25LM51245G Error codes
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*/
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#define MX25LM51245G_OK (0)
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#define MX25LM51245G_ERROR (-1)
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/**
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* @brief re-definition of legacy memory mapped functions
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*/
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#define MX25LM51245G_EnableMemoryMappedModeDTR MX25LM51245G_EnableDTRMemoryMappedMode
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#define MX25LM51245G_EnableMemoryMappedModeSTR MX25LM51245G_EnableSTRMemoryMappedMode
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/******************************************************************************
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* @brief MX25LM51245G Commands
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****************************************************************************/
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/*******************************************************************/
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/********************************* SPI ****************************/
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/*******************************************************************/
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/***** READ/WRITE MEMORY Operations with 3-Byte Address ****************************/
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#define MX25LM51245G_READ_CMD 0x03U /*!< Normal Read 3 Byte Address */
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#define MX25LM51245G_FAST_READ_CMD 0x0BU /*!< Fast Read 3 Byte Address */
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#define MX25LM51245G_PAGE_PROG_CMD 0x02U /*!< Page Program 3 Byte Address */
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#define MX25LM51245G_SUBSECTOR_ERASE_4K_CMD 0x20U /*!< SubSector Erase 4KB 3 Byte Address */
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#define MX25LM51245G_SECTOR_ERASE_64K_CMD 0xD8U /*!< Sector Erase 64KB 3 Byte Address */
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#define MX25LM51245G_BULK_ERASE_CMD 0x60U /*!< Bulk Erase */
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/***** READ/WRITE MEMORY Operations with 4-Byte Address ****************************/
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#define MX25LM51245G_4_BYTE_ADDR_READ_CMD 0x13U /*!< Normal Read 4 Byte address */
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#define MX25LM51245G_4_BYTE_ADDR_FAST_READ_CMD 0x0CU /*!< Fast Read 4 Byte address */
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#define MX25LM51245G_4_BYTE_PAGE_PROG_CMD 0x12U /*!< Page Program 4 Byte Address */
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#define MX25LM51245G_4_BYTE_SUBSECTOR_ERASE_4K_CMD 0x21U /*!< SubSector Erase 4KB 4 Byte Address */
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#define MX25LM51245G_4_BYTE_SECTOR_ERASE_64K_CMD 0xDCU /*!< Sector Erase 64KB 4 Byte Address */
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/***** Setting commands ************************************************************/
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#define MX25LM51245G_WRITE_ENABLE_CMD 0x06U /*!< Write Enable */
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#define MX25LM51245G_WRITE_DISABLE_CMD 0x04U /*!< Write Disable */
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#define MX25LM51245G_PROG_ERASE_SUSPEND_CMD 0xB0U /*!< Program/Erase suspend */
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#define MX25LM51245G_PROG_ERASE_RESUME_CMD 0x30U /*!< Program/Erase resume */
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#define MX25LM51245G_ENTER_DEEP_POWER_DOWN_CMD 0xB9U /*!< Enter deep power down */
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#define MX25LM51245G_SET_BURST_LENGTH_CMD 0xC0U /*!< Set burst length */
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#define MX25LM51245G_ENTER_SECURED_OTP_CMD 0xB1U /*!< Enter secured OTP) */
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#define MX25LM51245G_EXIT_SECURED_OTP_CMD 0xC1U /*!< Exit secured OTP) */
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/***** RESET commands ************************************************************/
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#define MX25LM51245G_NOP_CMD 0x00U /*!< No operation */
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#define MX25LM51245G_RESET_ENABLE_CMD 0x66U /*!< Reset Enable */
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#define MX25LM51245G_RESET_MEMORY_CMD 0x99U /*!< Reset Memory */
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/***** Register Commands (SPI) ****************************************************/
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#define MX25LM51245G_READ_ID_CMD 0x9FU /*!< Read IDentification */
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#define MX25LM51245G_READ_SERIAL_FLASH_DISCO_PARAM_CMD 0x5AU /*!< Read Serial Flash Discoverable Parameter */
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#define MX25LM51245G_READ_STATUS_REG_CMD 0x05U /*!< Read Status Register */
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#define MX25LM51245G_READ_CFG_REG_CMD 0x15U /*!< Read configuration Register */
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#define MX25LM51245G_WRITE_STATUS_REG_CMD 0x01U /*!< Write Status Register */
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#define MX25LM51245G_READ_CFG_REG2_CMD 0x71U /*!< Read configuration Register2 */
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#define MX25LM51245G_WRITE_CFG_REG2_CMD 0x72U /*!< Write configuration Register2 */
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#define MX25LM51245G_READ_FAST_BOOT_REG_CMD 0x16U /*!< Read fast boot Register */
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#define MX25LM51245G_WRITE_FAST_BOOT_REG_CMD 0x17U /*!< Write fast boot Register */
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#define MX25LM51245G_ERASE_FAST_BOOT_REG_CMD 0x18U /*!< Erase fast boot Register */
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#define MX25LM51245G_READ_SECURITY_REG_CMD 0x2BU /*!< Read security Register */
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#define MX25LM51245G_WRITE_SECURITY_REG_CMD 0x2FU /*!< Write security Register */
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#define MX25LM51245G_READ_LOCK_REG_CMD 0x2DU /*!< Read lock Register */
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#define MX25LM51245G_WRITE_LOCK_REG_CMD 0x2CU /*!< Write lock Register */
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#define MX25LM51245G_READ_DPB_REG_CMD 0xE0U /*!< Read DPB register */
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#define MX25LM51245G_WRITE_DPB_REG_CMD 0xE1U /*!< Write DPB register */
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#define MX25LM51245G_READ_SPB_STATUS_CMD 0xE2U /*!< Read SPB status */
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#define MX25LM51245G_WRITE_SPB_BIT_CMD 0xE3U /*!< SPB bit program */
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#define MX25LM51245G_ERASE_ALL_SPB_CMD 0xE4U /*!< Erase all SPB bit */
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#define MX25LM51245G_WRITE_PROTECT_SEL_CMD 0x68U /*!< Write Protect selection */
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#define MX25LM51245G_GANG_BLOCK_LOCK_CMD 0x7EU /*!< Gang block lock: whole chip write protect */
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#define MX25LM51245G_GANG_BLOCK_UNLOCK_CMD 0x98U /*!< Gang block unlock: whole chip write unprotect */
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#define MX25LM51245G_READ_PASSWORD_REGISTER_CMD 0x27U /*!< Read Password */
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#define MX25LM51245G_WRITE_PASSWORD_REGISTER_CMD 0x28U /*!< Write Password */
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#define MX25LM51245G_PASSWORD_UNLOCK_CMD 0x29U /*!< Unlock Password */
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/*******************************************************************/
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/********************************* OPI ****************************/
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/*******************************************************************/
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/***** READ/WRITE MEMORY Operations ****************************/
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#define MX25LM51245G_OCTA_READ_CMD 0xEC13U /*!< Octa IO Read */
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#define MX25LM51245G_OCTA_READ_DTR_CMD 0xEE11U /*!< Octa IO Read DTR */
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#define MX25LM51245G_OCTA_PAGE_PROG_CMD 0x12EDU /*!< Octa Page Program */
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#define MX25LM51245G_OCTA_SUBSECTOR_ERASE_4K_CMD 0x21DEU /*!< Octa SubSector Erase 4KB */
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#define MX25LM51245G_OCTA_SECTOR_ERASE_64K_CMD 0xDC23U /*!< Octa Sector Erase 64KB 3 */
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#define MX25LM51245G_OCTA_BULK_ERASE_CMD 0x609FU /*!< Octa Bulk Erase */
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/***** Setting commands ************************************************************/
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#define MX25LM51245G_OCTA_WRITE_ENABLE_CMD 0x06F9U /*!< Octa Write Enable */
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#define MX25LM51245G_OCTA_WRITE_DISABLE_CMD 0x04FBU /*!< Octa Write Disable */
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#define MX25LM51245G_OCTA_PROG_ERASE_SUSPEND_CMD 0xB04FU /*!< Octa Program/Erase suspend */
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#define MX25LM51245G_OCTA_PROG_ERASE_RESUME_CMD 0x30CFU /*!< Octa Program/Erase resume */
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#define MX25LM51245G_OCTA_ENTER_DEEP_POWER_DOWN_CMD 0xB946U /*!< Octa Enter deep power down */
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#define MX25LM51245G_OCTA_SET_BURST_LENGTH_CMD 0xC03FU /*!< Octa Set burst length */
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#define MX25LM51245G_OCTA_ENTER_SECURED_OTP_CMD 0xB14EU /*!< Octa Enter secured OTP) */
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#define MX25LM51245G_OCTA_EXIT_SECURED_OTP_CMD 0xC13EU /*!< Octa Exit secured OTP) */
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/***** RESET commands ************************************************************/
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#define MX25LM51245G_OCTA_NOP_CMD 0x00FFU /*!< Octa No operation */
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#define MX25LM51245G_OCTA_RESET_ENABLE_CMD 0x6699U /*!< Octa Reset Enable */
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#define MX25LM51245G_OCTA_RESET_MEMORY_CMD 0x9966U /*!< Octa Reset Memory */
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/***** Register Commands (OPI) ****************************************************/
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#define MX25LM51245G_OCTA_READ_ID_CMD 0x9F60U /*!< Octa Read IDentification */
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#define MX25LM51245G_OCTA_READ_SERIAL_FLASH_DISCO_PARAM_CMD 0x5AA5U /*!< Octa Read Serial Flash Discoverable Parameter */
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#define MX25LM51245G_OCTA_READ_STATUS_REG_CMD 0x05FAU /*!< Octa Read Status Register */
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#define MX25LM51245G_OCTA_READ_CFG_REG_CMD 0x15EAU /*!< Octa Read configuration Register */
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#define MX25LM51245G_OCTA_WRITE_STATUS_REG_CMD 0x01FEU /*!< Octa Write Status Register */
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#define MX25LM51245G_OCTA_READ_CFG_REG2_CMD 0x718EU /*!< Octa Read configuration Register2 */
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#define MX25LM51245G_OCTA_WRITE_CFG_REG2_CMD 0x728DU /*!< Octa Write configuration Register2 */
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#define MX25LM51245G_OCTA_READ_FAST_BOOT_REG_CMD 0x16E9U /*!< Octa Read fast boot Register */
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#define MX25LM51245G_OCTA_WRITE_FAST_BOOT_REG_CMD 0x17E8U /*!< Octa Write fast boot Register */
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#define MX25LM51245G_OCTA_ERASE_FAST_BOOT_REG_CMD 0x18E7U /*!< Octa Erase fast boot Register */
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#define MX25LM51245G_OCTA_READ_SECURITY_REG_CMD 0x2BD4U /*!< Octa Read security Register */
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#define MX25LM51245G_OCTA_WRITE_SECURITY_REG_CMD 0x2FD0U /*!< Octa Write security Register */
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#define MX25LM51245G_OCTA_READ_LOCK_REG_CMD 0x2DD2U /*!< Octa Read lock Register */
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#define MX25LM51245G_OCTA_WRITE_LOCK_REG_CMD 0x2CD3U /*!< Octa Write lock Register */
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#define MX25LM51245G_OCTA_READ_DPB_REG_CMD 0xE01FU /*!< Octa Read DPB register */
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#define MX25LM51245G_OCTA_WRITE_DPB_REG_CMD 0xE11EU /*!< Octa Write DPB register */
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#define MX25LM51245G_OCTA_READ_SPB_STATUS_CMD 0xE21DU /*!< Octa Read SPB status */
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#define MX25LM51245G_OCTA_WRITE_SPB_BIT_CMD 0xE31CU /*!< Octa SPB bit program */
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#define MX25LM51245G_OCTA_ERASE_ALL_SPB_CMD 0xE41BU /*!< Octa Erase all SPB bit */
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#define MX25LM51245G_OCTA_WRITE_PROTECT_SEL_CMD 0x6897U /*!< Octa Write Protect selection */
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#define MX25LM51245G_OCTA_GANG_BLOCK_LOCK_CMD 0x7E81U /*!< Octa Gang block lock: whole chip write protect */
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#define MX25LM51245G_OCTA_GANG_BLOCK_UNLOCK_CMD 0x9867U /*!< Octa Gang block unlock: whole chip write unprote*/
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#define MX25LM51245G_OCTA_READ_PASSWORD_REGISTER_CMD 0x27D8U /*!< Octa Read Password */
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#define MX25LM51245G_OCTA_WRITE_PASSWORD_REGISTER_CMD 0x28D7U /*!< Octa Write Password */
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#define MX25LM51245G_OCTA_PASSWORD_UNLOCK_CMD 0x29D6U /*!< Octa Unlock Password */
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/******************************************************************************
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* @brief MX25LM51245G Registers
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****************************************************************************/
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/* Status Register */
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#define MX25LM51245G_SR_WIP 0x01U /*!< Write in progress */
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#define MX25LM51245G_SR_WEL 0x02U /*!< Write enable latch */
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#define MX25LM51245G_SR_PB 0x3CU /*!< Block protected against program and erase operations */
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/* Configuration Register 1 */
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#define MX25LM51245G_CR1_ODS 0x07U /*!< Output driver strength */
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#define MX25LM51245G_CR1_TB 0x08U /*!< Top / bottom selected */
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#define MX25LM51245G_CR1_PBE 0x10U /*!< Preamble bit enable */
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/* Configuration Register 2 */
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/* Address : 0x00000000 */
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#define MX25LM51245G_CR2_REG1_ADDR 0x00000000U /*!< CR2 register address 0x00000000 */
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#define MX25LM51245G_CR2_SOPI 0x01U /*!< STR OPI Enable */
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#define MX25LM51245G_CR2_DOPI 0x02U /*!< DTR OPI Enable */
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/* Address : 0x00000200 */
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#define MX25LM51245G_CR2_REG2_ADDR 0x00000200U /*!< CR2 register address 0x00000200 */
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#define MX25LM51245G_CR2_DQSPRC 0x01U /*!< DTR DQS pre-cycle */
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#define MX25LM51245G_CR2_DOS 0x02U /*!< DQS on STR mode */
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/* Address : 0x00000300 */
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#define MX25LM51245G_CR2_REG3_ADDR 0x00000300U /*!< CR2 register address 0x00000300 */
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#define MX25LM51245G_CR2_DC 0x07U /*!< Dummy cycle */
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#define MX25LM51245G_CR2_DC_20_CYCLES 0x00U /*!< 20 Dummy cycles */
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#define MX25LM51245G_CR2_DC_18_CYCLES 0x01U /*!< 18 Dummy cycles */
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#define MX25LM51245G_CR2_DC_16_CYCLES 0x02U /*!< 16 Dummy cycles */
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#define MX25LM51245G_CR2_DC_14_CYCLES 0x03U /*!< 14 Dummy cycles */
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#define MX25LM51245G_CR2_DC_12_CYCLES 0x04U /*!< 12 Dummy cycles */
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#define MX25LM51245G_CR2_DC_10_CYCLES 0x05U /*!< 10 Dummy cycles */
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#define MX25LM51245G_CR2_DC_8_CYCLES 0x06U /*!< 8 Dummy cycles */
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#define MX25LM51245G_CR2_DC_6_CYCLES 0x07U /*!< 6 Dummy cycles */
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/* Address : 0x00000500 */
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#define MX25LM51245G_CR2_REG4_ADDR 0x00000500U /*!< CR2 register address 0x00000500 */
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#define MX25LM51245G_CR2_PPTSEL 0x01U /*!< Preamble pattern selection */
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/* Address : 0x40000000 */
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#define MX25LM51245G_CR2_REG5_ADDR 0x40000000U /*!< CR2 register address 0x40000000 */
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#define MX25LM51245G_CR2_DEFSOPI 0x01U /*!< Enable SOPI after power on reset */
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#define MX25LM51245G_CR2_DEFDOPI 0x02U /*!< Enable DOPI after power on reset */
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/* Security Register */
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#define MX25LM51245G_SECR_SOI 0x01U /*!< Secured OTP indicator */
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#define MX25LM51245G_SECR_LDSO 0x02U /*!< Lock-down secured OTP */
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#define MX25LM51245G_SECR_PSB 0x04U /*!< Program suspend bit */
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#define MX25LM51245G_SECR_ESB 0x08U /*!< Erase suspend bit */
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#define MX25LM51245G_SECR_P_FAIL 0x20U /*!< Program fail flag */
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#define MX25LM51245G_SECR_E_FAIL 0x40U /*!< Erase fail flag */
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#define MX25LM51245G_SECR_WPSEL 0x80U /*!< Write protection selection */
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/**
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* @}
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*/
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/** @defgroup MX25LM51245G_Exported_Types MX25LM51245G Exported Types
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* @{
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*/
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typedef struct {
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uint32_t FlashSize; /*!< Size of the flash */
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uint32_t EraseSectorSize; /*!< Size of sectors for the erase operation */
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uint32_t EraseSectorsNumber; /*!< Number of sectors for the erase operation */
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uint32_t EraseSubSectorSize; /*!< Size of subsector for the erase operation */
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uint32_t EraseSubSectorNumber; /*!< Number of subsector for the erase operation */
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uint32_t EraseSubSector1Size; /*!< Size of subsector 1 for the erase operation */
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uint32_t EraseSubSector1Number; /*!< Number of subsector 1 for the erase operation */
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uint32_t ProgPageSize; /*!< Size of pages for the program operation */
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uint32_t ProgPagesNumber; /*!< Number of pages for the program operation */
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} MX25LM51245G_Info_t;
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typedef enum {
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MX25LM51245G_SPI_MODE = 0, /*!< 1-1-1 commands, Power on H/W default setting */
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MX25LM51245G_OPI_MODE /*!< 8-8-8 commands */
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} MX25LM51245G_Interface_t;
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typedef enum {
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MX25LM51245G_STR_TRANSFER = 0, /*!< Single Transfer Rate */
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MX25LM51245G_DTR_TRANSFER /*!< Double Transfer Rate */
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} MX25LM51245G_Transfer_t;
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typedef enum {
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MX25LM51245G_ERASE_4K = 0, /*!< 4K size Sector erase */
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MX25LM51245G_ERASE_64K, /*!< 64K size Block erase */
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MX25LM51245G_ERASE_BULK /*!< Whole bulk erase */
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} MX25LM51245G_Erase_t;
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typedef enum {
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MX25LM51245G_3BYTES_SIZE = 0, /*!< 3 Bytes address mode */
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MX25LM51245G_4BYTES_SIZE /*!< 4 Bytes address mode */
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} MX25LM51245G_AddressSize_t;
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/**
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* @}
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*/
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/** @defgroup MX25LM51245G_Exported_Functions MX25LM51245G Exported Functions
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* @{
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*/
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/* Function by commands combined */
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int32_t MX25LM51245G_GetFlashInfo(MX25LM51245G_Info_t *pInfo);
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int32_t MX25LM51245G_AutoPollingMemReady(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate);
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/* Read/Write Array Commands **************************************************/
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int32_t MX25LM51245G_ReadSTR(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_AddressSize_t AddressSize, uint8_t *pData, uint32_t ReadAddr, uint32_t Size);
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int32_t MX25LM51245G_ReadDTR(OSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t ReadAddr, uint32_t Size);
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int32_t MX25LM51245G_PageProgram(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_AddressSize_t AddressSize, uint8_t *pData, uint32_t WriteAddr, uint32_t Size);
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int32_t MX25LM51245G_PageProgramDTR(OSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t WriteAddr, uint32_t Size);
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int32_t MX25LM51245G_BlockErase(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, MX25LM51245G_AddressSize_t AddressSize, uint32_t BlockAddress, MX25LM51245G_Erase_t BlockSize);
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int32_t MX25LM51245G_ChipErase(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate);
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int32_t MX25LM51245G_EnableMemoryMappedModeSTR(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_AddressSize_t AddressSize);
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int32_t MX25LM51245G_EnableMemoryMappedModeDTR(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode);
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int32_t MX25LM51245G_Suspend(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate);
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int32_t MX25LM51245G_Resume(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate);
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/* Register/Setting Commands **************************************************/
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int32_t MX25LM51245G_WriteEnable(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate);
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int32_t MX25LM51245G_WriteDisable(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate);
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int32_t MX25LM51245G_ReadStatusRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t *Value);
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int32_t MX25LM51245G_WriteStatusRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t Value);
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int32_t MX25LM51245G_WriteCfgRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t Value);
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int32_t MX25LM51245G_ReadCfgRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t *Value);
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int32_t MX25LM51245G_WriteCfg2Register(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint32_t WriteAddr, uint8_t Value);
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int32_t MX25LM51245G_ReadCfg2Register(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint32_t ReadAddr, uint8_t *Value);
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int32_t MX25LM51245G_WriteSecurityRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t Value);
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int32_t MX25LM51245G_ReadSecurityRegister(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t *Value);
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/* ID/Security Commands *******************************************************/
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int32_t MX25LM51245G_ReadID(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate, uint8_t *ID);
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/* Reset Commands *************************************************************/
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int32_t MX25LM51245G_ResetEnable(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate);
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int32_t MX25LM51245G_ResetMemory(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate);
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int32_t MX25LM51245G_NoOperation(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate);
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int32_t MX25LM51245G_EnterPowerDown(OSPI_HandleTypeDef *Ctx, MX25LM51245G_Interface_t Mode, MX25LM51245G_Transfer_t Rate);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* MX25LM51245G_H */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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