184 lines
7.0 KiB
C
184 lines
7.0 KiB
C
/**
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******************************************************************************
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* @file s70kl1281.h
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* @author MCD Application Team
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* @brief This file contains all the description of the S70KL1281 Octal memory.
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2020 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef S70KL1281_H
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#define S70KL1281_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "s70kl1281_conf.h"
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/** @addtogroup BSP
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* @{
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*/
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/** @addtogroup Components
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* @{
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*/
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/** @addtogroup S70KL1281
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* @{
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*/
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/** @defgroup S70KL1281_Exported_Types
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup S70KL1281_Exported_Constants
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* @{
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*/
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/**
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* @brief S70KL1281 Configuration
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*/
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#define S70KL1281_RAM_SIZE 0x1000000 /* 128 MBits => 16 MBytes */
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/**
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* @brief MX25LM51245G Error codes
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*/
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#define S70KL1281_OK (0)
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#define S70KL1281_ERROR (-1)
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/******************************************************************************
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* @brief S70KL1281 Registers
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****************************************************************************/
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/* Device Identification Register 0 */
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#define S70KL1281_DIR0_ADDRESS 0x00000000U
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#define S70KL1281_DIR0_MANUFACTURER 0x000FU /*!< Manufacturer */
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#define S70KL1281_DIR0_CADC 0x00F0U /*!< Column Address Bit Count */
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#define S70KL1281_DIR0_RABC 0x1F00U /*!< Row Address Bit Count */
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#define S70KL1281_DIR0_DADDR 0xC000U /*!< Die Address */
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#define S70KL1281_DIR0_DADDR_DIE_0 0x0000U /*!< Die 0 Address */
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#define S70KL1281_DIR0_DADDR_DIE_1 0x4000U /*!< Die 1 Address */
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#define S70KL1281_DIR0_DADDR_DIE_2 0x8000U /*!< Die 2 Address */
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#define S70KL1281_DIR0_DADDR_DIE_3 0xC000U /*!< Die 3 Address */
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/* Device Identification Register 1 */
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#define S70KL1281_DIR1_ADDRESS 0x00000002U
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#define S70KL1281_DIR1_DTYPE 0x000FU /*!< Device Type */
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#define S70KL1281_DIR1_DTYPE_HYPERRAM 0x0000U /*!< HyperRAM Device Type */
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/* Configuration Register 0 */
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#define S70KL1281_CR0_ADDRESS 0x00001000U
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#define S70KL1281_CR0_BLENGTH 0x0003U /*!< Burst length */
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#define S70KL1281_CR0_BLENGTH_128 0x0000U /*!< 128 bytes burst length */
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#define S70KL1281_CR0_BLENGTH_64 0x0001U /*!< 64 bytes burst length */
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#define S70KL1281_CR0_BLENGTH_16 0x0002U /*!< 16 bytes burst length */
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#define S70KL1281_CR0_BLENGTH_32 0x0003U /*!< 32 bytes burst length */
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#define S70KL1281_CR0_HBE 0x0004U /*!< Hybrid burst enable */
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#define S70KL1281_CR0_FLE 0x0008U /*!< Fixed latency enable */
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#define S70KL1281_CR0_IL 0x00F0U /*!< Initial latency */
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#define S70KL1281_CR0_IL_5_CLOCK 0x0000U /*!< 5 clock latency */
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#define S70KL1281_CR0_IL_6_CLOCK 0x0010U /*!< 6 clock latency */
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#define S70KL1281_CR0_IL_3_CLOCK 0x00E0U /*!< 3 clock latency */
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#define S70KL1281_CR0_IL_4_CLOCK 0x00F0U /*!< 4 clock latency */
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#define S70KL1281_CR0_DS 0x7000U /*!< Drive strength */
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#define S70KL1281_CR0_DS_34 0x0000U /*!< 34 ohms drive strength */
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#define S70KL1281_CR0_DS_115 0x1000U /*!< 115 ohms drive strength */
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#define S70KL1281_CR0_DS_67 0x2000U /*!< 67 ohms drive strength */
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#define S70KL1281_CR0_DS_46 0x3000U /*!< 46 ohms drive strength */
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#define S70KL1281_CR0_DS_34_2 0x4000U /*!< 34 ohms drive strength */
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#define S70KL1281_CR0_DS_27 0x5000U /*!< 27 ohms drive strength */
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#define S70KL1281_CR0_DS_22 0x6000U /*!< 22 ohms drive strength */
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#define S70KL1281_CR0_DS_19 0x7000U /*!< 19 ohms drive strength */
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#define S70KL1281_CR0_DPDE 0x8000U /*!< Deep Power down enable */
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/* Configuration Register 1 */
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#define S70KL1281_CR1_ADDRESS 0x00001002U
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#define S70KL1281_CR1_DRI 0x0003U /*!< Distributed refresh interval */
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#define S70KL1281_CR1_DRI_2_TIMES 0x0000U /*!< 2 times default distributed refresh interval */
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#define S70KL1281_CR1_DRI_4_TIMES 0x0001U /*!< 4 times default distributed refresh interval */
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#define S70KL1281_CR1_DRI_DEFAULT 0x0002U /*!< Default distributed refresh interval */
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#define S70KL1281_CR1_DRI_1_5_TIMES 0x0003U /*!< 1.5 times default distributed refresh interval */
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/**
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* @}
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*/
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/** @defgroup S70KL1281_Exported_Types S70KL1281Exported Types
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* @{
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*/
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typedef enum {
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S70KL1281_BURST_16_BYTES = S70KL1281_CR0_BLENGTH_16,
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S70KL1281_BURST_32_BYTES = S70KL1281_CR0_BLENGTH_32,
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S70KL1281_BURST_64_BYTES = S70KL1281_CR0_BLENGTH_64,
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S70KL1281_BURST_128_BYTES = S70KL1281_CR0_BLENGTH_128
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} S70KL1281_BurstLength_t;
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/**
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* @}
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*/
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/** @defgroup S70KL1281_Exported_Functions
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* @{
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*/
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/* Read/Write Array Commands **************************************************/
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int32_t S70KL1281_Read(OSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t ReadAddr, uint32_t Size);
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int32_t S70KL1281_Read_DMA(OSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t ReadAddr, uint32_t Size);
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int32_t S70KL1281_Write(OSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t WriteAddr, uint32_t Size);
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int32_t S70KL1281_Write_DMA(OSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t WriteAddr, uint32_t Size);
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int32_t S70KL1281_EnableMemoryMappedMode(OSPI_HandleTypeDef *Ctx);
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/* Register/Setting Commands **************************************************/
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int32_t S70KL1281_ReadCfgReg0(OSPI_HandleTypeDef *Ctx, uint16_t *Value);
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int32_t S70KL1281_WriteCfgReg0(OSPI_HandleTypeDef *Ctx, uint16_t Value, uint32_t LatencyMode, uint32_t InitialLatency);
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int32_t S70KL1281_ReadCfgReg1(OSPI_HandleTypeDef *Ctx, uint16_t *Value);
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int32_t S70KL1281_WriteCfgReg1(OSPI_HandleTypeDef *Ctx, uint16_t Value, uint32_t LatencyMode, uint32_t InitialLatency);
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/* ID Commands ****************************************************************/
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int32_t S70KL1281_ReadID(OSPI_HandleTypeDef *Ctx, uint16_t *ID);
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/* Power down Commands ********************************************************/
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int32_t S70KL1281_EnterPowerDown(OSPI_HandleTypeDef *Ctx, uint32_t LatencyMode, uint32_t InitialLatency);
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int32_t S70KL1281_LeavePowerDown(OSPI_HandleTypeDef *Ctx);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* S70KL1281_H */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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