14 Commits

Author SHA1 Message Date
8a5c800fd3 - BlockingFifo implemented
- get_interface_by_address() added
- HTTP server initials added
- code added to strip away padding on processing the IP layer by shrinking overall packet size
- load of TCP fixes and improvements
- TCP stream interface added
- TCP window destroy() added and some bugs fixed
2023-11-22 20:55:50 +01:00
0add109430 implicit type conversions fixed 2023-10-25 17:41:36 +02:00
ab8d45932f Timestamping and bunch of bugfix and optimization
- Timestamping management added
- Errors due to reading uninitialized data in ARP fixed
- EthInterface reworked, incoming packet notification and payload readout separated (through which fixing concurrent access problems)
- RX and TX offloads added
- Capability to add a packet sieve layer without prior registration of specific packet class added (this makes it possible to register arbitrary EtherType connection blocks, for example)
2023-04-27 09:38:26 +02:00
30af96f4c9 packet header processing cache added 2023-02-28 12:18:43 +01:00
ac5fc9c529 -IP reassembler added
-PcktSieve special return functionality added
-ARP multicast learning bug fixed
-include guards have been refactored
-Doxygen style tweaked
2023-02-04 11:04:26 +01:00
51696f7341 - MemoryPool allocation-deallocation bug fixed
- generic Queue implemented
- PacketRegistry allocation bug fixed
- TCP implementation initials
- ALIGN to type macros added
2023-01-17 08:19:29 +01:00
05288d7a3c - ARP cache auto lookup feature added
- IGMPv2 capabilities added (report membership, leave group)
- ICMP capabilities added (ping)
- Tx Message Queue added
2023-01-14 14:24:56 +01:00
905b455bb3 ARP cache added (initial implementation); DHCP basics 2022-12-14 22:07:16 +01:00
3e1a2174a6 Load of advancements 2022-11-07 21:51:18 +01:00
49fa57b63e Packet header linked list initially implemented 2022-11-04 07:54:57 +01:00
Wiesner András
0f3c8ca601 Ethernet II, IPv4, UDP packet parsers added (not complete) 2022-11-03 16:58:17 +01:00
1654523577 PcktRegistry initial steps 2022-11-03 07:47:10 +01:00
4f13160f52 MemoryPool implemented 2022-11-02 22:43:18 +01:00
1d80cebbce initial 2022-10-27 21:03:58 +02:00