forked from epagris/FreeRTOS-Kernel
Updates to CM4_MPU IAR port
- System calls are now only allowed from kernel code. This change can be turned on or off using configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY. - MPU is disabled before reprogramming it and enabled afterwards to be compliant with ARM recommendations.
This commit is contained in:
Gaurav Aggarwal
parent
b27fb82bc1
commit
96b6746364
@ -33,8 +33,8 @@
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#include <intrinsics.h>
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/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
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all the API functions to use the MPU wrappers. That should only be done when
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task.h is included from an application file. */
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* all the API functions to use the MPU wrappers. That should only be done when
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* task.h is included from an application file. */
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#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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/* Scheduler includes. */
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@ -43,8 +43,6 @@ task.h is included from an application file. */
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#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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#warning This is not yet a documented port as it has not been fully tested, so no demo projects that use this port are provided.
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#ifndef __ARMVFP__
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#error This port can only be used when the project options are configured to enable hardware floating point support.
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#endif
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@ -94,7 +92,7 @@ task.h is included from an application file. */
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#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
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r0p1 port. */
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* r0p1 port. */
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#define portCPUID ( * ( ( volatile uint32_t * ) 0xE000ed00 ) )
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#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
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#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
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@ -222,10 +220,10 @@ static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )
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{
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/* Simulate the stack frame as it would be created by a context switch
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interrupt. */
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* interrupt. */
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/* Offset added to account for the way the MCU uses the stack on entry/exit
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of interrupts, and to ensure alignment. */
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* of interrupts, and to ensure alignment. */
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pxTopOfStack--;
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*pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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@ -239,7 +237,7 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
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*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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/* A save method is being used that requires each task to maintain its
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own exec return value. */
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* own exec return value. */
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pxTopOfStack--;
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*pxTopOfStack = portINITIAL_EXC_RETURN;
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@ -261,10 +259,16 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
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void vPortSVCHandler_C( uint32_t *pulParam )
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{
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uint8_t ucSVCNumber;
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uint32_t ulPC;
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#if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
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extern uint32_t __syscalls_flash_start__[];
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extern uint32_t __syscalls_flash_end__[];
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#endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
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/* The stack contains: r0, r1, r2, r3, r12, r14, the return address and
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xPSR. The first argument (r0) is pulParam[ 0 ]. */
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ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];
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/* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first
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* argument (r0) is pulParam[ 0 ]. */
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ulPC = pulParam[ portOFFSET_TO_PC ];
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ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
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switch( ucSVCNumber )
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{
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case portSVC_START_SCHEDULER : portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;
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@ -273,14 +277,31 @@ uint8_t ucSVCNumber;
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case portSVC_YIELD : portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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/* Barriers are normally not required
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but do ensure the code is completely
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within the specified behaviour for the
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architecture. */
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* but do ensure the code is completely
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* within the specified behaviour for the
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* architecture. */
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__asm volatile( "dsb" ::: "memory" );
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__asm volatile( "isb" );
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break;
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#if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
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case portSVC_RAISE_PRIVILEGE : /* Only raise the privilege, if the
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* svc was raised from any of the
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* system calls. */
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if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
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ulPC <= ( uint32_t ) __syscalls_flash_end__ )
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{
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__asm volatile
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(
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" mrs r1, control \n" /* Obtain current control value. */
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" bic r1, r1, #1 \n" /* Set privilege bit. */
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" msr control, r1 \n" /* Write back new control value. */
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::: "r1", "memory"
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);
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}
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break;
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#else
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case portSVC_RAISE_PRIVILEGE : __asm volatile
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(
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" mrs r1, control \n" /* Obtain current control value. */
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@ -289,6 +310,7 @@ uint8_t ucSVCNumber;
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::: "r1", "memory"
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);
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break;
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#endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
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default : /* Unknown SVC call. */
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break;
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@ -302,12 +324,12 @@ uint8_t ucSVCNumber;
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BaseType_t xPortStartScheduler( void )
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{
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/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
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See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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* See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
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/* This port can be used on all revisions of the Cortex-M7 core other than
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the r0p1 parts. r0p1 parts should use the port from the
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/source/portable/GCC/ARM_CM7/r0p1 directory. */
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* the r0p1 parts. r0p1 parts should use the port from the
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* /source/portable/GCC/ARM_CM7/r0p1 directory. */
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configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
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configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
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@ -318,15 +340,15 @@ BaseType_t xPortStartScheduler( void )
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volatile uint8_t ucMaxPriorityValue;
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/* Determine the maximum priority from which ISR safe FreeRTOS API
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functions can be called. ISR safe functions are those that end in
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"FromISR". FreeRTOS maintains separate thread and ISR API functions to
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ensure interrupt entry is as fast and simple as possible.
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* functions can be called. ISR safe functions are those that end in
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* "FromISR". FreeRTOS maintains separate thread and ISR API functions to
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* ensure interrupt entry is as fast and simple as possible.
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Save the interrupt priority value that is about to be clobbered. */
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ulOriginalPriority = *pucFirstUserPriorityRegister;
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/* Determine the number of priority bits available. First write to all
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possible bits. */
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* possible bits. */
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*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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/* Read the value back to see how many bits stuck. */
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@ -336,7 +358,7 @@ BaseType_t xPortStartScheduler( void )
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ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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/* Calculate the maximum acceptable priority group value for the number
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of bits read back. */
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* of bits read back. */
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ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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{
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@ -347,8 +369,8 @@ BaseType_t xPortStartScheduler( void )
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#ifdef __NVIC_PRIO_BITS
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{
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/* Check the CMSIS configuration that defines the number of
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priority bits matches the number of priority bits actually queried
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from the hardware. */
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* priority bits matches the number of priority bits actually queried
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* from the hardware. */
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configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
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}
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#endif
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@ -356,19 +378,19 @@ BaseType_t xPortStartScheduler( void )
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#ifdef configPRIO_BITS
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{
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/* Check the FreeRTOS configuration that defines the number of
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priority bits matches the number of priority bits actually queried
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from the hardware. */
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* priority bits matches the number of priority bits actually queried
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* from the hardware. */
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configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
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}
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#endif
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/* Shift the priority group value back to its position within the AIRCR
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register. */
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* register. */
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ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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/* Restore the clobbered interrupt priority register to its original
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value. */
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* value. */
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*pucFirstUserPriorityRegister = ulOriginalPriority;
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}
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#endif /* conifgASSERT_DEFINED */
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@ -381,7 +403,7 @@ BaseType_t xPortStartScheduler( void )
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prvSetupMPU();
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/* Start the timer that generates the tick ISR. Interrupts are disabled
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here already. */
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* here already. */
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vPortSetupTimerInterrupt();
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/* Initialise the critical nesting count ready for the first task. */
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@ -404,7 +426,7 @@ BaseType_t xPortStartScheduler( void )
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void vPortEndScheduler( void )
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{
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/* Not implemented in ports where there is nothing to return to.
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Artificially force an assert. */
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* Artificially force an assert. */
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configASSERT( uxCriticalNesting == 1000UL );
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}
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/*-----------------------------------------------------------*/
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@ -419,10 +441,10 @@ void vPortEnterCritical( void )
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vPortResetPrivilege( xRunningPrivileged );
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/* This is not the interrupt safe version of the enter critical function so
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assert() if it is being called from an interrupt context. Only API
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functions that end in "FromISR" can be used in an interrupt. Only assert if
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the critical nesting count is 1 to protect against recursive calls if the
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assert function also uses a critical section. */
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* assert() if it is being called from an interrupt context. Only API
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* functions that end in "FromISR" can be used in an interrupt. Only assert if
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* the critical nesting count is 1 to protect against recursive calls if the
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* assert function also uses a critical section. */
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if( uxCriticalNesting == 1 )
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{
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configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
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@ -449,16 +471,16 @@ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
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void xPortSysTickHandler( void )
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{
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/* The SysTick runs at the lowest interrupt priority, so when this interrupt
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executes all interrupts must be unmasked. There is therefore no need to
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save and then restore the interrupt mask value as its value is already
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known. */
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* executes all interrupts must be unmasked. There is therefore no need to
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* save and then restore the interrupt mask value as its value is already
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* known. */
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portDISABLE_INTERRUPTS();
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{
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/* Increment the RTOS tick. */
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if( xTaskIncrementTick() != pdFALSE )
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{
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/* A context switch is required. Context switching is performed in
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the PendSV interrupt. Pend the PendSV interrupt. */
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* the PendSV interrupt. Pend the PendSV interrupt. */
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portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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}
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}
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@ -504,8 +526,8 @@ extern uint32_t __privileged_data_end__[];
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( portMPU_REGION_ENABLE );
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/* Setup the first 16K for privileged only access (even though less
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than 10K is actually being used). This is where the kernel code is
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placed. */
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* than 10K is actually being used). This is where the kernel code is
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* placed. */
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portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
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( portMPU_REGION_VALID ) |
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( portPRIVILEGED_FLASH_REGION );
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@ -516,7 +538,7 @@ extern uint32_t __privileged_data_end__[];
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( portMPU_REGION_ENABLE );
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/* Setup the privileged data RAM region. This is where the kernel data
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is placed. */
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* is placed. */
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portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
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( portMPU_REGION_VALID ) |
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( portPRIVILEGED_RAM_REGION );
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@ -527,7 +549,7 @@ extern uint32_t __privileged_data_end__[];
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( portMPU_REGION_ENABLE );
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/* By default allow everything to access the general peripherals. The
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system peripherals and registers are protected. */
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* system peripherals and registers are protected. */
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portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |
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( portMPU_REGION_VALID ) |
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( portGENERAL_PERIPHERALS_REGION );
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@ -550,7 +572,7 @@ static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
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uint32_t ulRegionSize, ulReturnValue = 4;
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/* 32 is the smallest region size, 31 is the largest valid value for
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ulReturnValue. */
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* ulReturnValue. */
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for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
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{
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if( ulActualSizeInBytes <= ulRegionSize )
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@ -564,7 +586,7 @@ uint32_t ulRegionSize, ulReturnValue = 4;
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}
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/* Shift the code by one before returning so it can be written directly
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into the the correct bit position of the attribute register. */
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* into the the correct bit position of the attribute register. */
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return ( ulReturnValue << 1UL );
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}
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/*-----------------------------------------------------------*/
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@ -593,7 +615,7 @@ uint32_t ul;
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( portMPU_REGION_ENABLE );
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/* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
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just removed the privileged only parameters. */
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* just removed the privileged only parameters. */
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xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
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( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
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( portMPU_REGION_VALID ) |
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@ -615,9 +637,9 @@ uint32_t ul;
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else
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{
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/* This function is called automatically when the task is created - in
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which case the stack region parameters will be valid. At all other
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times the stack parameters will not be valid and it is assumed that the
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stack region has already been configured. */
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* which case the stack region parameters will be valid. At all other
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* times the stack parameters will not be valid and it is assumed that the
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* stack region has already been configured. */
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if( ulStackDepth > 0 )
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{
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/* Define the region that allows access to the stack. */
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@ -640,8 +662,8 @@ uint32_t ul;
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if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
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{
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/* Translate the generic region definition contained in
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xRegions into the CM3 specific MPU settings that are then
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stored in xMPUSettings. */
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* xRegions into the CM3 specific MPU settings that are then
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* stored in xMPUSettings. */
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xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
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( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
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( portMPU_REGION_VALID ) |
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@ -682,66 +704,46 @@ uint32_t ul;
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ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
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/* The following assertion will fail if a service routine (ISR) for
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an interrupt that has been assigned a priority above
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configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
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function. ISR safe FreeRTOS API functions must *only* be called
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from interrupts that have been assigned a priority at or below
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configMAX_SYSCALL_INTERRUPT_PRIORITY.
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* an interrupt that has been assigned a priority above
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* configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
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* function. ISR safe FreeRTOS API functions must *only* be called
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* from interrupts that have been assigned a priority at or below
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* configMAX_SYSCALL_INTERRUPT_PRIORITY.
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Numerically low interrupt priority numbers represent logically high
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interrupt priorities, therefore the priority of the interrupt must
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be set to a value equal to or numerically *higher* than
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configMAX_SYSCALL_INTERRUPT_PRIORITY.
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* Numerically low interrupt priority numbers represent logically high
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* interrupt priorities, therefore the priority of the interrupt must
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* be set to a value equal to or numerically *higher* than
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* configMAX_SYSCALL_INTERRUPT_PRIORITY.
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Interrupts that use the FreeRTOS API must not be left at their
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default priority of zero as that is the highest possible priority,
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which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
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and therefore also guaranteed to be invalid.
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* Interrupts that use the FreeRTOS API must not be left at their
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* default priority of zero as that is the highest possible priority,
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* which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
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* and therefore also guaranteed to be invalid.
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FreeRTOS maintains separate thread and ISR API functions to ensure
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interrupt entry is as fast and simple as possible.
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* FreeRTOS maintains separate thread and ISR API functions to ensure
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* interrupt entry is as fast and simple as possible.
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The following links provide detailed information:
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http://www.freertos.org/RTOS-Cortex-M3-M4.html
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http://www.freertos.org/FAQHelp.html */
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* The following links provide detailed information:
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* http://www.freertos.org/RTOS-Cortex-M3-M4.html
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* http://www.freertos.org/FAQHelp.html */
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configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
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}
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/* Priority grouping: The interrupt controller (NVIC) allows the bits
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that define each interrupt's priority to be split between bits that
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define the interrupt's pre-emption priority bits and bits that define
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the interrupt's sub-priority. For simplicity all bits must be defined
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to be pre-emption priority bits. The following assertion will fail if
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this is not the case (if some bits represent a sub-priority).
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* that define each interrupt's priority to be split between bits that
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* define the interrupt's pre-emption priority bits and bits that define
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* the interrupt's sub-priority. For simplicity all bits must be defined
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* to be pre-emption priority bits. The following assertion will fail if
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* this is not the case (if some bits represent a sub-priority).
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If the application only uses CMSIS libraries for interrupt
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configuration then the correct setting can be achieved on all Cortex-M
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devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
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scheduler. Note however that some vendor specific peripheral libraries
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assume a non-zero priority group setting, in which cases using a value
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of zero will result in unpredictable behaviour. */
|
||||
* If the application only uses CMSIS libraries for interrupt
|
||||
* configuration then the correct setting can be achieved on all Cortex-M
|
||||
* devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
|
||||
* scheduler. Note however that some vendor specific peripheral libraries
|
||||
* assume a non-zero priority group setting, in which cases using a value
|
||||
* of zero will result in unpredictable behaviour. */
|
||||
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
|
||||
}
|
||||
|
||||
#endif /* configASSERT_DEFINED */
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
@ -78,12 +78,26 @@ xPortPendSVHandler:
|
||||
ldr r0, [r1]
|
||||
/* Move onto the second item in the TCB... */
|
||||
add r1, r1, #4
|
||||
|
||||
dmb /* Complete outstanding transfers before disabling MPU. */
|
||||
ldr r2, =0xe000ed94 /* MPU_CTRL register. */
|
||||
ldr r3, [r2] /* Read the value of MPU_CTRL. */
|
||||
bic r3, r3, #1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
|
||||
str r3, [r2] /* Disable MPU. */
|
||||
|
||||
/* Region Base Address register. */
|
||||
ldr r2, =0xe000ed9c
|
||||
/* Read 4 sets of MPU registers. */
|
||||
ldmia r1!, {r4-r11}
|
||||
/* Write 4 sets of MPU registers. */
|
||||
stmia r2!, {r4-r11}
|
||||
|
||||
ldr r2, =0xe000ed94 /* MPU_CTRL register. */
|
||||
ldr r3, [r2] /* Read the value of MPU_CTRL. */
|
||||
orr r3, r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
|
||||
str r3, [r2] /* Enable MPU. */
|
||||
dsb /* Force memory writes before continuing. */
|
||||
|
||||
/* Pop the registers that are not automatically saved on exception entry. */
|
||||
ldmia r0!, {r3-r11, r14}
|
||||
msr control, r3
|
||||
@ -151,12 +165,26 @@ vPortRestoreContextOfFirstTask:
|
||||
ldr r0, [r1]
|
||||
/* Move onto the second item in the TCB... */
|
||||
add r1, r1, #4
|
||||
|
||||
dmb /* Complete outstanding transfers before disabling MPU. */
|
||||
ldr r2, =0xe000ed94 /* MPU_CTRL register. */
|
||||
ldr r3, [r2] /* Read the value of MPU_CTRL. */
|
||||
bic r3, r3, #1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
|
||||
str r3, [r2] /* Disable MPU. */
|
||||
|
||||
/* Region Base Address register. */
|
||||
ldr r2, =0xe000ed9c
|
||||
/* Read 4 sets of MPU registers. */
|
||||
ldmia r1!, {r4-r11}
|
||||
/* Write 4 sets of MPU registers. */
|
||||
stmia r2!, {r4-r11}
|
||||
|
||||
ldr r2, =0xe000ed94 /* MPU_CTRL register. */
|
||||
ldr r3, [r2] /* Read the value of MPU_CTRL. */
|
||||
orr r3, r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
|
||||
str r3, [r2] /* Enable MPU. */
|
||||
dsb /* Force memory writes before continuing. */
|
||||
|
||||
/* Pop the registers that are not automatically saved on exception entry. */
|
||||
ldmia r0!, {r3-r11, r14}
|
||||
msr control, r3
|
||||
|
||||
@ -25,6 +25,7 @@
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
|
||||
#ifndef PORTMACRO_H
|
||||
#define PORTMACRO_H
|
||||
|
||||
@ -75,12 +76,13 @@ typedef unsigned long UBaseType_t;
|
||||
#define portUSING_MPU_WRAPPERS 1
|
||||
#define portPRIVILEGE_BIT ( 0x80000000UL )
|
||||
|
||||
#define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL )
|
||||
#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL )
|
||||
#define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL )
|
||||
#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL )
|
||||
#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
|
||||
#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
|
||||
#define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL )
|
||||
#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL )
|
||||
#define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL )
|
||||
#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL )
|
||||
#define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL )
|
||||
#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
|
||||
#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
|
||||
|
||||
#define portUNPRIVILEGED_FLASH_REGION ( 0UL )
|
||||
#define portPRIVILEGED_FLASH_REGION ( 1UL )
|
||||
@ -106,7 +108,6 @@ typedef struct MPU_SETTINGS
|
||||
xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];
|
||||
} xMPU_SETTINGS;
|
||||
|
||||
|
||||
/* Architecture specifics. */
|
||||
#define portSTACK_GROWTH ( -1 )
|
||||
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
||||
@ -119,6 +120,7 @@ typedef struct MPU_SETTINGS
|
||||
#define portSVC_RAISE_PRIVILEGE 2
|
||||
|
||||
/* Scheduler utilities. */
|
||||
|
||||
#define portYIELD() __asm volatile ( " SVC %0 \n" :: "i" (portSVC_YIELD) : "memory" )
|
||||
#define portYIELD_WITHIN_API() \
|
||||
{ \
|
||||
@ -132,7 +134,6 @@ typedef struct MPU_SETTINGS
|
||||
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
|
||||
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD_WITHIN_API()
|
||||
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Architecture specific optimisations. */
|
||||
@ -214,11 +215,19 @@ extern void vResetPrivilege( void );
|
||||
#define portRESET_PRIVILEGE() vResetPrivilege()
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
|
||||
#warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security."
|
||||
#define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0
|
||||
#endif
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
|
||||
the source code because to do so would cause other compilers to generate
|
||||
warnings. */
|
||||
#pragma diag_suppress=Pe191
|
||||
#pragma diag_suppress=Pa082
|
||||
#pragma diag_suppress=Be006
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user