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Author SHA1 Message Date
Richard Barry
3153131fa7 Add Dornerworks attribution to makefiles that build the Freedom Studio RISC-V project. 2019-02-12 02:43:28 +00:00
Richard Barry
7e08fd6d07 Add makefiles that build the FreedomStudio project (provided by Dornerworks - thanks). 2019-02-11 19:44:13 +00:00
Richard Barry
fb73829148 Ensure eTaskGetState() is brought in automatically if INCLUDE_xTaskAbortDelay is set to 1, as it is a dependency of eTaskGetState(). 
Added the portTASK_FUNCTION_PROTO macros around the timer task, as the macros are already used by the idle task.
Add a PDF of the RISC-V documentation into the repo as the web page is not yet live.
 2019-02-08 01:18:08 +00:00
Richard Barry
df5952f655 Add xTaskGetIdleRunTimeCounter() API function to return the run time stats counter for the idle task - useful for POSIX time implementations. 2019-01-21 23:39:48 +00:00
Gaurav Aggarwal
817783d75c Copyright updates from Cadence. 
e1df894752
 2019-01-16 19:01:25 +00:00
Richard Barry
a4941ac5db Update main.c() for the WIN32-MingW project so the trace recorder is initialized even when the simple blinky demo is used - otherwise the trace recorder causes an exception as it is used without first being initialized. 2019-01-07 19:40:13 +00:00
Richard Barry
80df5cd517 Update the pin mux setup on the Vega board demo to enable the LED. 2018-12-31 20:14:34 +00:00
Richard Barry
11d9c440b8 Move the 'generic' version of freertos_risc_v_chip_specific_extensions.h back to a sub-directory as having it in the RISC-V port's base directory was causing SoftConsole to pick up the wrong version (for an unknown reason). 
Add a project for the Vega board's RI5CY core.
 2018-12-31 18:19:52 +00:00
Richard Barry
e2af102c80 Re-org of RISC-V file structure and naming step 2. 2018-12-30 23:53:47 +00:00
Richard Barry
818eeccc0c Re-org of RISC-V file structure and naming step 1. 2018-12-30 23:20:26 +00:00
Richard Barry
3474e750fa Create folder to hold RISC-V chip specific extensions. 2018-12-30 23:15:37 +00:00
Richard Barry
db750d0c82 Update RSIC-V port layer after testing saving and receiving of chip specific registers. 2018-12-30 23:11:40 +00:00
Richard Barry
60b133b2c6 Move the RISC-V pxPortInitialiseStack() implementation to the assembly port file from the C port file so it can have access to the number of chip specific registers it needs to save space for on the stack. 2018-12-30 20:00:43 +00:00
Richard Barry
911a1de273 Correct accidental deletion in GenQTest.c. 2018-12-28 03:38:27 +00:00
Richard Barry
d369110167 Allow the size of the stack used by many of the standard demo/test tasks to be overridden by FreeRTOSConfig.h settings. 
Update the Freedom Studio RISC-V project so the 'full' build configuration is now functional.
 2018-12-28 00:44:18 +00:00
Richard Barry
178fe4f143 Update the Freedom Studio RISC-V project so the gdbinit options are now specified on the command line. 2018-12-27 04:57:49 +00:00
Richard Barry
e5daf23d75 Update Freedom Studio RISC-V demo for the latest GCC RISC-V port - not yet tested. 2018-12-27 04:34:08 +00:00
Richard Barry
80f6f3e59b Retarget Softconsole RISC-V demo from IGLOO2 to Renode as it can have more RAM and therefore have more test tasks running. 2018-12-24 17:48:10 +00:00
Richard Barry
ce36928ea8 Rename directories in the RISC-V port. 2018-12-24 17:37:02 +00:00
Richard Barry
2181c0375e Backup Microsemi Renode project before adding a build configuration for the target hardware. 2018-12-19 02:56:13 +00:00
Richard Barry
8d213b42f2 Add vTimerSetReloadMode() calls to the code coverage tests. 2018-12-17 23:19:23 +00:00
Richard Barry
6edabbe7ea Update the the MPU simulator project to exercise the timer API. 2018-12-17 22:06:58 +00:00
Richard Barry
148f588f56 Remove "FromISR' functions from the list of functions that switch to a privileged mode as IRQs are privileged already. 
Add the vTimerSetReloadMode() API function.
 2018-12-17 22:04:18 +00:00
Richard Barry
8285ca6b5f Update RISC-V_IGLOO2_Creative_SoftConsole demo to make use of new RISC-V porting layer structure and exercise some external interrupts - all tests currently passing in Renode. 2018-12-17 00:01:36 +00:00
Richard Barry
101806906d Rework RISC-V portASM.S to make it easier to add in chip specific RISC-V extensions and accommodate chips that don't include the CLINT. 2018-12-16 23:59:49 +00:00
Richard Barry
7cc42b2ab6 Save changes to the RISC-V port layer before making changes necessary to support pulpino too: 
+ Switch positions of the asm functions used to start the kernel and handle traps to enable one to reference to the other.
+ Handle external interrupts (working with Renode emulator).
+ The _sp linker variable is now called __freertos_irq_stack_top.
 2018-12-16 20:21:29 +00:00
Richard Barry
866635d2ad Microsemi RISC-V project: 
Reorganize project to separate Microsemi code into its own directory.
    Add many more demo and tests.
 2018-12-10 20:55:32 +00:00
Richard Barry
6b37800ade Backup checkin of MiFive demo running in ReNode emulator. 2018-12-10 05:28:05 +00:00
Richard Barry
9a136a52df Backup check in of the Microsemi IGLOO2 Creative Board RISC-V demo - still a work in progress. 2018-12-04 01:27:06 +00:00
Richard Barry
4b9dd38d1c Backup checking of the Freedom Studio RISC-V project - still a work in progress. 2018-12-04 01:25:53 +00:00
Richard Barry
65f7a2dc19 Update RISC-V port to use a separate interrupt stack. 2018-12-04 01:23:41 +00:00
Richard Barry
e85ea96f78 Some efficiency improvements in Risc-V port. 2018-11-28 19:35:40 +00:00
Richard Barry
dc99300fa9 First task running in RISC-V-Qemu-sifive_e-FreedomStudio demo. 2018-11-24 20:59:07 +00:00
Richard Barry
d0ef322b13 Add kernel code to the RISC-V-Qemu-sifive_e-FreedomStudio demo. 2018-11-24 04:42:20 +00:00
Richard Barry
f7102f2342 Add a starting point for a Freedom Studio Risc V project. 2018-11-24 03:48:55 +00:00
Richard Barry
db64297487 Provide each Risc V task with an initial mstatus register value. 2018-11-20 20:12:35 +00:00
Richard Barry
8cef339aec Update Risc-V port to use environment call in place of software interrupt - still very much a work in progress. 2018-11-19 06:01:29 +00:00
Richard Barry
baee711cb6 Continue work on Risc V port. 2018-11-06 02:04:28 +00:00
Richard Barry
74d0d16aab Update xTaskRemoveFromEventList() so when tickless idle is used prvResetNextTaskUnblockTime() only gets called if the scheduler is not locked, as it would get called when the scheduler is unlocked in any case. 2018-11-05 19:35:54 +00:00
Richard Barry
55ff89373a Update the method used to detect if a timer is active. Previously the timer was deemed to be inactive if it was not referenced from a list. However, when a timer is updated it is temporarily removed from, then re-added to a list, so now the timer's active status is stored separately. 2018-10-24 21:37:59 +00:00
Richard Barry
6fab2b9e0d Add xTaskGetApplicationTaskTagFromISR(), which is an interrupt safe version of xTaskGetApplicationTaskTagFrom(). 2018-10-08 15:10:18 +00:00
Gaurav Aggarwal
1af80854e6 Fix Xtensa project file and some documentation improvements. 2018-10-02 23:54:51 +00:00
Richard Barry
c6de0001fa Added uxTaskGetStackHighWaterMark2(), which is the same as uxTaskGetStackHighWaterMark() other than the return type. 
Allows the task name parameter passed into xTaskCreate() to be NULL.
 2018-09-30 21:50:05 +00:00
Richard Barry
e3dc5e934b RISC-V tasks now context switching to each other using taskYIELD() - not fully tested yet. 2018-09-27 17:25:17 +00:00
Richard Barry
2bcb1ab02b Add trap handler to RISC-V port so there is no dependency on third party code. 2018-09-23 03:52:23 +00:00
Richard Barry
32f35e9130 RISC-V: 
Added code to setup the timer interrupt - not tested yet.
Added the taskYIELD() implementation - so far just checked it generates an interrupt.
 2018-09-12 16:33:05 +00:00
Richard Barry
b11eb3a59c RISC-V work in progress: 
+ Initialise task stack.
    + Successfully jump to start of first task.
 2018-09-10 20:50:05 +00:00
Richard Barry
0c0f0d0f8f Minor synching - no functional changes. 2018-09-07 22:24:51 +00:00
Richard Barry
ab49c6ae04 Very minor formatting changes, and remove legacy link to V8 upgrade information. 2018-09-07 21:35:05 +00:00
Richard Barry
92ae8e7aff Update version numbers ready for release. 2018-09-07 18:13:20 +00:00