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Gaurav-Aggarwal-AWS 9efca75d1e
Riscv re-factoring (#444) 
* Refactor RISCV port

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Changes to make re-factoring work on ESP32-C3

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Remove alignment and place handlers in separate sections

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Correct section names

This is needed so that the assemblers correctly recognizes functions.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Move mtvec programming to the application

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Refactor mtimer udpate code

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Move critical nesting to port layer

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Respect configTASK_RETURN_ADDRESS

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Formatting changes

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
2022-01-26 17:55:01 -08:00
..
ARM7_AT91FR40008
Normalize files with mixed line endings (introduced in commit 3a413d1)
2021-06-01 17:55:18 -07:00
ARM7_AT91SAM7S
Normalize files with mixed line endings (introduced in commit 3a413d1)
2021-06-01 17:55:18 -07:00
ARM7_LPC23xx
Normalize files with mixed line endings (introduced in commit 3a413d1)
2021-06-01 17:55:18 -07:00
ARM7_LPC2000
Normalize files with mixed line endings (introduced in commit 3a413d1)
2021-06-01 17:55:18 -07:00
ARM_CA9
fix typo (#399)
2021-10-06 15:32:07 -07:00
ARM_CA53_64_BIT
fix alignment exception for ullPortInterruptNesting. (#317)
2021-12-29 13:53:10 -07:00
ARM_CA53_64_BIT_SRE
Update comments for the ARM_CA53_64_BIT_SRE port (#403)
2021-10-16 13:45:03 -07:00
ARM_CM0
Normalize files with mixed line endings (introduced in commit 3a413d1)
2021-06-01 17:55:18 -07:00
ARM_CM3
fix typo (#399)
2021-10-06 15:32:07 -07:00
ARM_CM3_MPU
Add option to disable unprivileged critical sections
2021-11-15 15:09:12 -08:00
ARM_CM4_MPU
Add option to disable unprivileged critical sections
2021-11-15 15:09:12 -08:00
ARM_CM4F
fix typo (#399)
2021-10-06 15:32:07 -07:00
ARM_CM7
fix typo (#399)
2021-10-06 15:32:07 -07:00
ARM_CM23
Fix free secure context for Cortex-M23 ports
2021-09-10 16:44:36 -07:00
ARM_CM23_NTZ/non_secure
Associate secure context with task handle
2021-09-10 16:44:36 -07:00
ARM_CM33
Implement secure stack sealing as per ARM's recommendation
2021-09-10 16:44:36 -07:00
ARM_CM33_NTZ/non_secure
Associate secure context with task handle
2021-09-10 16:44:36 -07:00
ARM_CR5
fix typo (#399)
2021-10-06 15:32:07 -07:00
ARM_CRx_No_GIC
Normalize files with mixed line endings (introduced in commit 3a413d1)
2021-06-01 17:55:18 -07:00
ATMega323
Normalize files with mixed line endings (introduced in commit 3a413d1)
2021-06-01 17:55:18 -07:00
AVR32_UC3
Update license text for ports that were previously missed.
2021-05-27 19:57:55 -07:00
AVR_AVRDx
Remove AVR ports from main repo (#394)
2021-09-14 19:25:46 -07:00
AVR_Mega0
Remove AVR ports from main repo (#394)
2021-09-14 19:25:46 -07:00
ColdFire_V2
Normalize files with mixed line endings (introduced in commit 3a413d1)
2021-06-01 17:55:18 -07:00
CORTUS_APS3
Normalize files with mixed line endings (introduced in commit 3a413d1)
2021-06-01 17:55:18 -07:00
H8S2329
Normalize files with mixed line endings (introduced in commit 3a413d1)
2021-06-01 17:55:18 -07:00
HCS12
Normalize files with mixed line endings (introduced in commit 3a413d1)
2021-06-01 17:55:18 -07:00
IA32_flat
Normalize files with mixed line endings (introduced in commit 3a413d1)
2021-06-01 17:55:18 -07:00
MCF5235
Replace two dashes and one whitespace with their corresponding ASCII characters. (#362)
2021-06-30 15:07:55 -07:00
MicroBlaze
Normalize files with mixed line endings (introduced in commit 3a413d1)
2021-06-01 17:55:18 -07:00
MicroBlazeV8
Normalize files with mixed line endings (introduced in commit 3a413d1)
2021-06-01 17:55:18 -07:00
MicroBlazeV9
Normalize files with mixed line endings (introduced in commit 3a413d1)
2021-06-01 17:55:18 -07:00
MSP430F449
Normalize files with mixed line endings (introduced in commit 3a413d1)
2021-06-01 17:55:18 -07:00
NiosII
Fix: Interrut Handler Register Function and Exception Process (#41)
2021-12-28 10:54:23 -07:00
PPC405_Xilinx
Normalize files with mixed line endings (introduced in commit 3a413d1)
2021-06-01 17:55:18 -07:00
PPC440_Xilinx
Normalize files with mixed line endings (introduced in commit 3a413d1)
2021-06-01 17:55:18 -07:00
RISC-V
Riscv re-factoring (#444)
2022-01-26 17:55:01 -08:00
RL78
Normalize files with mixed line endings (introduced in commit 3a413d1)
2021-06-01 17:55:18 -07:00
RX100
Fix GCC/RX100 function naming error. (#440)
2022-01-13 10:30:26 -08:00
RX200
Normalize files with mixed line endings (introduced in commit 3a413d1)
2021-06-01 17:55:18 -07:00
RX600
Normalize files with mixed line endings (introduced in commit 3a413d1)
2021-06-01 17:55:18 -07:00
RX600v2
Normalize files with mixed line endings (introduced in commit 3a413d1)
2021-06-01 17:55:18 -07:00
RX700v3_DPFPU
Add SPDX-License-Identifier: MIT to MIT licensed files.
2021-05-27 19:57:55 -07:00
STR75x
Normalize files with mixed line endings (introduced in commit 3a413d1)
2021-06-01 17:55:18 -07:00
TriCore_1782
Normalize files with mixed line endings (introduced in commit 3a413d1)
2021-06-01 17:55:18 -07:00