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Gaurav Aggarwal ccaa0f4d6e Pre-allocate secure-side context structures 
This commit improves ARMv8-M security by pre-allocating secure-side task
context structures and changing how tasks reference a secure-side
context structure when calling a secure function. The new configuration
constant secureconfigMAX_SECURE_CONTEXTS sets the number of secure
context structures to pre-allocate. secureconfigMAX_SECURE_CONTEXTS
defaults to 8 if left undefined.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
2021-09-10 16:44:36 -07:00
..
ARM7_AT91FR40008
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ARM7_AT91SAM7S
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ARM7_LPC23xx
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ARM7_LPC2000
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ARM_CA9
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ARM_CA53_64_BIT
Normalize files with mixed line endings (introduced in commit 3a413d1)
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ARM_CA53_64_BIT_SRE
Add Cortex-A53 port with system register interface for CPU interface access (#357)
2021-06-22 18:51:58 -07:00
ARM_CM0
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ARM_CM3
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ARM_CM3_MPU
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ARM_CM4_MPU
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ARM_CM4F
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ARM_CM7
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ARM_CM23
Pre-allocate secure-side context structures
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ARM_CM23_NTZ/non_secure
Warning fixes. (#356)
2021-07-20 12:55:49 -07:00
ARM_CM33
Pre-allocate secure-side context structures
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ARM_CM33_NTZ/non_secure
Warning fixes. (#356)
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ARM_CR5
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ARM_CRx_No_GIC
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ATMega323
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2021-06-01 17:55:18 -07:00
AVR32_UC3
Update license text for ports that were previously missed.
2021-05-27 19:57:55 -07:00
AVR_AVRDx
Add SPDX-License-Identifier: MIT to MIT licensed files.
2021-05-27 19:57:55 -07:00
AVR_Mega0
Add SPDX-License-Identifier: MIT to MIT licensed files.
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ColdFire_V2
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CORTUS_APS3
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H8S2329
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HCS12
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IA32_flat
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MCF5235
Replace two dashes and one whitespace with their corresponding ASCII characters. (#362)
2021-06-30 15:07:55 -07:00
MicroBlaze
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MicroBlazeV8
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MicroBlazeV9
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MSP430F449
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NiosII
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PPC405_Xilinx
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PPC440_Xilinx
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RISC-V
Add freertos_risc_v_chip_specific_extensions.h for 64-bit ports (#385)
2021-09-01 15:38:07 -07:00
RL78
Normalize files with mixed line endings (introduced in commit 3a413d1)
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RX100
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RX200
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RX600
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RX600v2
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RX700v3_DPFPU
Add SPDX-License-Identifier: MIT to MIT licensed files.
2021-05-27 19:57:55 -07:00
STR75x
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TriCore_1782
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