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Update History.txt as per the PR feedback

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Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
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Gaurav Aggarwal 2022-09-16 22:15:49 +05:30 committed by Gaurav-Aggarwal-AWS
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@ -2,28 +2,39 @@ Changes between FreeRTOS V10.4.6 and FreeRTOS V10.5.0 released September 16 2022
Documentation and download available at https://www.FreeRTOS.org/ Documentation and download available at https://www.FreeRTOS.org/
+ ARMv7-M and ARMv8-M MPU ports: It is possible for a third party that + ARMv7-M and ARMv8-M MPU ports: It was possible for a third party that
already independently gained the ability to execute injected code to already independently gained the ability to execute injected code to
read from or write to arbitrary addresses by passing a negative argument read from or write to arbitrary addresses by passing a negative argument
as the xIndex parameter to pvTaskGetThreadLocalStoragePointer() or as the xIndex parameter to pvTaskGetThreadLocalStoragePointer() or
vTaskSetThreadLocalStoragePointer respectively. vTaskSetThreadLocalStoragePointer respectively. A check has been added to
ensure that passing a negative argument as the xIndex parameter does not
cause arbitrary read or write.
We thank Certibit Consulting, LLC for reporting this issue. We thank Certibit Consulting, LLC for reporting this issue.
+ ARMv7-M and ARMv8-M MPU ports: It is possible for an unprivileged task to + ARMv7-M and ARMv8-M MPU ports: It was possible for an unprivileged task
invoke any function with privilege by passing it as a parameter to to invoke any function with privilege by passing it as a parameter to
MPU_xTaskCreate, MPU_xTaskCreateStatic, MPU_xTimerCreate, MPU_xTaskCreate, MPU_xTaskCreateStatic, MPU_xTimerCreate,
MPU_xTimerCreateStatic, or MPU_xTimerPendFunctionCall. MPU_xTimerCreateStatic, or MPU_xTimerPendFunctionCall. MPU_xTaskCreate
We thank Huazhong University of Science and Technology for reporting this issue. and MPU_xTaskCreateStatic have been updated to only allow creation of
+ ARMv7-M and ARMv8-M MPU ports: It is possible for a third party that has unprivileged tasks. MPU_xTimerCreate, MPU_xTimerCreateStatic and
MPU_xTimerPendFunctionCall APIs have been removed.
We thank Huazhong University of Science and Technology for reporting
this issue.
+ ARMv7-M and ARMv8-M MPU ports: It was possible for a third party that
already independently gained the ability to execute injected code to already independently gained the ability to execute injected code to
achieve further privilege escalation by branching directly inside a achieve further privilege escalation by branching directly inside a
FreeRTOS MPU API wrapper function with a manually crafted stack frame. FreeRTOS MPU API wrapper function with a manually crafted stack frame.
The local stack variable `xRunningPrivileged` has been removed so that
a manually crafted stack frame cannot be used for privilege escalation
by branching directly inside a FreeRTOS MPU API wrapper.
We thank Certibit Consulting, LLC, Huazhong University of Science and We thank Certibit Consulting, LLC, Huazhong University of Science and
Technology and the SecLab team at Northeastern University for reporting Technology and the SecLab team at Northeastern University for reporting
this issue. this issue.
+ ARMv7-M MPU ports: It is possible to configure overlapping memory + ARMv7-M MPU ports: It was possible to configure overlapping memory
protection unit (MPU) regions such that an unprivileged task can access protection unit (MPU) regions such that an unprivileged task could access
privileged data. privileged data. The kernel now uses highest numbered MPU regions for
We thank the SecLab team at Northeastern University for reporting this issue. kernel protections to prevent such MPU configurations.
We thank the SecLab team at Northeastern University for reporting this
issue.
+ Add support for ARM Cortex-M55. + Add support for ARM Cortex-M55.
+ Add support for ARM Cortex-M85. Contributed by @gbrtth. + Add support for ARM Cortex-M85. Contributed by @gbrtth.
+ Add vectored mode interrupt support to the RISC-V port. + Add vectored mode interrupt support to the RISC-V port.