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Remove __NVIC_PRIO_BITS and configPRIO_BITS check in port (#683)

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* Remove __NVIC_PRIO_BITS and configPRIO_BITS check in CM3, CM4 and ARMv8.
* Add hardware not implemented bits check. These bits should be zero.

---------

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
This commit is contained in:
chinglee-iot 2023-06-08 10:52:08 +08:00 committed by GitHub
parent d3c289fe5b
commit 4a35c97fec
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
37 changed files with 148 additions and 961 deletions
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33
portable/ARMv8M/non_secure/port.c
View File

@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
/* The interrupt priority bits are not modelled in QEMU and the assert that
* checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
* Therefore, this assert is not adding any value for QEMU targets. The config
* option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
* `FreeRTOSConfig.h` for QEMU targets. */
#ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
{
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
}
#endif /* __NVIC_PRIO_BITS */
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == configPRIO_BITS );
}
#endif /* configPRIO_BITS */
}
#endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

26
portable/CCS/ARM_CM3/port.c
View File

@ -249,6 +249,10 @@ BaseType_t xPortStartScheduler( void )
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -285,28 +289,6 @@ BaseType_t xPortStartScheduler( void )
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is at least as many as specified in the CMSIS
* __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS );
}
#endif
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is at least as many as specified in the FreeRTOS
* configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits >= configPRIO_BITS );
}
#endif
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

26
portable/CCS/ARM_CM4F/port.c
View File

@ -268,6 +268,10 @@ BaseType_t xPortStartScheduler( void )
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -304,28 +308,6 @@ BaseType_t xPortStartScheduler( void )
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is at least as many as specified in the CMSIS
* __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS );
}
#endif
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is at least as many as specified in the FreeRTOS
* configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits >= configPRIO_BITS );
}
#endif
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

33
portable/GCC/ARM_CM23/non_secure/port.c
View File

@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
/* The interrupt priority bits are not modelled in QEMU and the assert that
* checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
* Therefore, this assert is not adding any value for QEMU targets. The config
* option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
* `FreeRTOSConfig.h` for QEMU targets. */
#ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
{
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
}
#endif /* __NVIC_PRIO_BITS */
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == configPRIO_BITS );
}
#endif /* configPRIO_BITS */
}
#endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

33
portable/GCC/ARM_CM23_NTZ/non_secure/port.c
View File

@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
/* The interrupt priority bits are not modelled in QEMU and the assert that
* checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
* Therefore, this assert is not adding any value for QEMU targets. The config
* option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
* `FreeRTOSConfig.h` for QEMU targets. */
#ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
{
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
}
#endif /* __NVIC_PRIO_BITS */
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == configPRIO_BITS );
}
#endif /* configPRIO_BITS */
}
#endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

26
portable/GCC/ARM_CM3/port.c
View File

@ -292,6 +292,10 @@ BaseType_t xPortStartScheduler( void )
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -328,28 +332,6 @@ BaseType_t xPortStartScheduler( void )
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is at least as many as specified in the CMSIS
* __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS );
}
#endif
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is at least as many as specified in the FreeRTOS
* configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits >= configPRIO_BITS );
}
#endif
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

33
portable/GCC/ARM_CM33/non_secure/port.c
View File

@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
/* The interrupt priority bits are not modelled in QEMU and the assert that
* checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
* Therefore, this assert is not adding any value for QEMU targets. The config
* option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
* `FreeRTOSConfig.h` for QEMU targets. */
#ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
{
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
}
#endif /* __NVIC_PRIO_BITS */
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == configPRIO_BITS );
}
#endif /* configPRIO_BITS */
}
#endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

33
portable/GCC/ARM_CM33_NTZ/non_secure/port.c
View File

@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
/* The interrupt priority bits are not modelled in QEMU and the assert that
* checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
* Therefore, this assert is not adding any value for QEMU targets. The config
* option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
* `FreeRTOSConfig.h` for QEMU targets. */
#ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
{
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
}
#endif /* __NVIC_PRIO_BITS */
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == configPRIO_BITS );
}
#endif /* configPRIO_BITS */
}
#endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

33
portable/GCC/ARM_CM35P/non_secure/port.c
View File

@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
/* The interrupt priority bits are not modelled in QEMU and the assert that
* checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
* Therefore, this assert is not adding any value for QEMU targets. The config
* option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
* `FreeRTOSConfig.h` for QEMU targets. */
#ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
{
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
}
#endif /* __NVIC_PRIO_BITS */
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == configPRIO_BITS );
}
#endif /* configPRIO_BITS */
}
#endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

33
portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
View File

@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
/* The interrupt priority bits are not modelled in QEMU and the assert that
* checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
* Therefore, this assert is not adding any value for QEMU targets. The config
* option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
* `FreeRTOSConfig.h` for QEMU targets. */
#ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
{
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
}
#endif /* __NVIC_PRIO_BITS */
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == configPRIO_BITS );
}
#endif /* configPRIO_BITS */
}
#endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

26
portable/GCC/ARM_CM3_MPU/port.c
View File

@ -415,6 +415,10 @@ BaseType_t xPortStartScheduler( void )
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -451,28 +455,6 @@ BaseType_t xPortStartScheduler( void )
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is at least as many as specified in the CMSIS
* __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS );
}
#endif
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is at least as many as specified in the FreeRTOS
* configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits >= configPRIO_BITS );
}
#endif
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

26
portable/GCC/ARM_CM4F/port.c
View File

@ -335,6 +335,10 @@ BaseType_t xPortStartScheduler( void )
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -371,28 +375,6 @@ BaseType_t xPortStartScheduler( void )
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is at least as many as specified in the CMSIS
* __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS );
}
#endif
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is at least as many as specified in the FreeRTOS
* configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits >= configPRIO_BITS );
}
#endif
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

26
portable/GCC/ARM_CM4_MPU/port.c
View File

@ -458,6 +458,10 @@ BaseType_t xPortStartScheduler( void )
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -494,28 +498,6 @@ BaseType_t xPortStartScheduler( void )
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried
* from hardware is at least as many as specified in the
* CMSIS __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS );
}
#endif
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried
* from hardware is at least as many as specified in the
* FreeRTOS configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits >= configPRIO_BITS );
}
#endif
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

33
portable/GCC/ARM_CM55/non_secure/port.c
View File

@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
/* The interrupt priority bits are not modelled in QEMU and the assert that
* checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
* Therefore, this assert is not adding any value for QEMU targets. The config
* option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
* `FreeRTOSConfig.h` for QEMU targets. */
#ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
{
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
}
#endif /* __NVIC_PRIO_BITS */
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == configPRIO_BITS );
}
#endif /* configPRIO_BITS */
}
#endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

33
portable/GCC/ARM_CM55_NTZ/non_secure/port.c
View File

@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
/* The interrupt priority bits are not modelled in QEMU and the assert that
* checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
* Therefore, this assert is not adding any value for QEMU targets. The config
* option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
* `FreeRTOSConfig.h` for QEMU targets. */
#ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
{
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
}
#endif /* __NVIC_PRIO_BITS */
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == configPRIO_BITS );
}
#endif /* configPRIO_BITS */
}
#endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

26
portable/GCC/ARM_CM7/r0p1/port.c
View File

@ -323,6 +323,10 @@ BaseType_t xPortStartScheduler( void )
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -359,28 +363,6 @@ BaseType_t xPortStartScheduler( void )
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is at least as many as specified in the CMSIS
* __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS );
}
#endif
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is at least as many as specified in the FreeRTOS
* configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits >= configPRIO_BITS );
}
#endif
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

33
portable/GCC/ARM_CM85/non_secure/port.c
View File

@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
/* The interrupt priority bits are not modelled in QEMU and the assert that
* checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
* Therefore, this assert is not adding any value for QEMU targets. The config
* option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
* `FreeRTOSConfig.h` for QEMU targets. */
#ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
{
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
}
#endif /* __NVIC_PRIO_BITS */
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == configPRIO_BITS );
}
#endif /* configPRIO_BITS */
}
#endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

33
portable/GCC/ARM_CM85_NTZ/non_secure/port.c
View File

@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
/* The interrupt priority bits are not modelled in QEMU and the assert that
* checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
* Therefore, this assert is not adding any value for QEMU targets. The config
* option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
* `FreeRTOSConfig.h` for QEMU targets. */
#ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
{
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
}
#endif /* __NVIC_PRIO_BITS */
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == configPRIO_BITS );
}
#endif /* configPRIO_BITS */
}
#endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

33
portable/IAR/ARM_CM23/non_secure/port.c
View File

@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
/* The interrupt priority bits are not modelled in QEMU and the assert that
* checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
* Therefore, this assert is not adding any value for QEMU targets. The config
* option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
* `FreeRTOSConfig.h` for QEMU targets. */
#ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
{
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
}
#endif /* __NVIC_PRIO_BITS */
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == configPRIO_BITS );
}
#endif /* configPRIO_BITS */
}
#endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

33
portable/IAR/ARM_CM23_NTZ/non_secure/port.c
View File

@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
/* The interrupt priority bits are not modelled in QEMU and the assert that
* checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
* Therefore, this assert is not adding any value for QEMU targets. The config
* option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
* `FreeRTOSConfig.h` for QEMU targets. */
#ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
{
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
}
#endif /* __NVIC_PRIO_BITS */
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == configPRIO_BITS );
}
#endif /* configPRIO_BITS */
}
#endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

26
portable/IAR/ARM_CM3/port.c
View File

@ -241,6 +241,10 @@ BaseType_t xPortStartScheduler( void )
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -277,28 +281,6 @@ BaseType_t xPortStartScheduler( void )
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is at least as many as specified in the CMSIS
* __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS );
}
#endif
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is at least as many as specified in the FreeRTOS
* configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits >= configPRIO_BITS );
}
#endif
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

33
portable/IAR/ARM_CM33/non_secure/port.c
View File

@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
/* The interrupt priority bits are not modelled in QEMU and the assert that
* checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
* Therefore, this assert is not adding any value for QEMU targets. The config
* option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
* `FreeRTOSConfig.h` for QEMU targets. */
#ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
{
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
}
#endif /* __NVIC_PRIO_BITS */
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == configPRIO_BITS );
}
#endif /* configPRIO_BITS */
}
#endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

33
portable/IAR/ARM_CM33_NTZ/non_secure/port.c
View File

@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
/* The interrupt priority bits are not modelled in QEMU and the assert that
* checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
* Therefore, this assert is not adding any value for QEMU targets. The config
* option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
* `FreeRTOSConfig.h` for QEMU targets. */
#ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
{
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
}
#endif /* __NVIC_PRIO_BITS */
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == configPRIO_BITS );
}
#endif /* configPRIO_BITS */
}
#endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

33
portable/IAR/ARM_CM35P/non_secure/port.c
View File

@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
/* The interrupt priority bits are not modelled in QEMU and the assert that
* checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
* Therefore, this assert is not adding any value for QEMU targets. The config
* option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
* `FreeRTOSConfig.h` for QEMU targets. */
#ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
{
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
}
#endif /* __NVIC_PRIO_BITS */
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == configPRIO_BITS );
}
#endif /* configPRIO_BITS */
}
#endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

33
portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
View File

@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
/* The interrupt priority bits are not modelled in QEMU and the assert that
* checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
* Therefore, this assert is not adding any value for QEMU targets. The config
* option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
* `FreeRTOSConfig.h` for QEMU targets. */
#ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
{
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
}
#endif /* __NVIC_PRIO_BITS */
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == configPRIO_BITS );
}
#endif /* configPRIO_BITS */
}
#endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

26
portable/IAR/ARM_CM4F/port.c
View File

@ -279,6 +279,10 @@ BaseType_t xPortStartScheduler( void )
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -315,28 +319,6 @@ BaseType_t xPortStartScheduler( void )
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is at least as many as specified in the CMSIS
* __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS );
}
#endif
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is at least as many as specified in the FreeRTOS
* configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits >= configPRIO_BITS );
}
#endif
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

26
portable/IAR/ARM_CM4F_MPU/port.c
View File

@ -393,6 +393,10 @@ BaseType_t xPortStartScheduler( void )
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -429,28 +433,6 @@ BaseType_t xPortStartScheduler( void )
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is at least as many as specified in the CMSIS
* __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS );
}
#endif
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is at least as many as specified in the FreeRTOS
* configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits >= configPRIO_BITS );
}
#endif
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

33
portable/IAR/ARM_CM55/non_secure/port.c
View File

@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
/* The interrupt priority bits are not modelled in QEMU and the assert that
* checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
* Therefore, this assert is not adding any value for QEMU targets. The config
* option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
* `FreeRTOSConfig.h` for QEMU targets. */
#ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
{
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
}
#endif /* __NVIC_PRIO_BITS */
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == configPRIO_BITS );
}
#endif /* configPRIO_BITS */
}
#endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

33
portable/IAR/ARM_CM55_NTZ/non_secure/port.c
View File

@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
/* The interrupt priority bits are not modelled in QEMU and the assert that
* checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
* Therefore, this assert is not adding any value for QEMU targets. The config
* option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
* `FreeRTOSConfig.h` for QEMU targets. */
#ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
{
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
}
#endif /* __NVIC_PRIO_BITS */
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == configPRIO_BITS );
}
#endif /* configPRIO_BITS */
}
#endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

26
portable/IAR/ARM_CM7/r0p1/port.c
View File

@ -267,6 +267,10 @@ BaseType_t xPortStartScheduler( void )
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -303,28 +307,6 @@ BaseType_t xPortStartScheduler( void )
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is at least as many as specified in the CMSIS
* __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS );
}
#endif
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is at least as many as specified in the FreeRTOS
* configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits >= configPRIO_BITS );
}
#endif
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

33
portable/IAR/ARM_CM85/non_secure/port.c
View File

@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
/* The interrupt priority bits are not modelled in QEMU and the assert that
* checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
* Therefore, this assert is not adding any value for QEMU targets. The config
* option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
* `FreeRTOSConfig.h` for QEMU targets. */
#ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
{
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
}
#endif /* __NVIC_PRIO_BITS */
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == configPRIO_BITS );
}
#endif /* configPRIO_BITS */
}
#endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

33
portable/IAR/ARM_CM85_NTZ/non_secure/port.c
View File

@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
/* The interrupt priority bits are not modelled in QEMU and the assert that
* checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
* Therefore, this assert is not adding any value for QEMU targets. The config
* option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
* `FreeRTOSConfig.h` for QEMU targets. */
#ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
{
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
}
#endif /* __NVIC_PRIO_BITS */
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits == configPRIO_BITS );
}
#endif /* configPRIO_BITS */
}
#endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

26
portable/MikroC/ARM_CM4F/port.c
View File

@ -329,6 +329,10 @@ BaseType_t xPortStartScheduler( void )
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -365,28 +369,6 @@ BaseType_t xPortStartScheduler( void )
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is at least as many as specified in the CMSIS
* __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS );
}
#endif
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is at least as many as specified in the FreeRTOS
* configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits >= configPRIO_BITS );
}
#endif
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

26
portable/RVDS/ARM_CM3/port.c
View File

@ -294,6 +294,10 @@ BaseType_t xPortStartScheduler( void )
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -330,28 +334,6 @@ BaseType_t xPortStartScheduler( void )
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is at least as many as specified in the CMSIS
* __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS );
}
#endif
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is at least as many as specified in the FreeRTOS
* configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits >= configPRIO_BITS );
}
#endif
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

26
portable/RVDS/ARM_CM4F/port.c
View File

@ -360,6 +360,10 @@ BaseType_t xPortStartScheduler( void )
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -396,28 +400,6 @@ BaseType_t xPortStartScheduler( void )
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is at least as many as specified in the CMSIS
* __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS );
}
#endif
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is at least as many as specified in the FreeRTOS
* configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits >= configPRIO_BITS );
}
#endif
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

26
portable/RVDS/ARM_CM4_MPU/port.c
View File

@ -453,6 +453,10 @@ BaseType_t xPortStartScheduler( void )
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -489,28 +493,6 @@ BaseType_t xPortStartScheduler( void )
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is at least as many as specified in the CMSIS
* __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS );
}
#endif
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is at least as many as specified in the FreeRTOS
* configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits >= configPRIO_BITS );
}
#endif
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

26
portable/RVDS/ARM_CM7/r0p1/port.c
View File

@ -344,6 +344,10 @@ BaseType_t xPortStartScheduler( void )
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
/* Check that the bits not implemented bits in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
@ -380,28 +384,6 @@ BaseType_t xPortStartScheduler( void )
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
}
#ifdef __NVIC_PRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is at least as many as specified in the CMSIS
* __NVIC_PRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS );
}
#endif
#ifdef configPRIO_BITS
{
/*
* Check that the number of implemented priority bits queried from
* hardware is at least as many as specified in the FreeRTOS
* configPRIO_BITS configuration macro.
*/
configASSERT( ulImplementedPrioBits >= configPRIO_BITS );
}
#endif
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;