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Serial Data Out + + + Serial Data In + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AXI General Purpose IO + General Purpose Input/Output (GPIO) core for the AXI bus. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GPIO1 Data IO + + + GPIO2 Data IO + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AXI General Purpose IO + General Purpose Input/Output (GPIO) core for the AXI bus. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GPIO1 Data IO + + + GPIO2 Data IO + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AXI 10/100 Ethernet MAC Lite + 'IEEE Std. 802.3 MII interface MAC with AXI interface, lightweight implementation' + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Ethernet PHY Management Data + + + Ethernet PHY Management Clock + + + Ethernet Transmit Data Output + + + Ethernet Transmit Enable + + + Ethernet Transmit Clock Input + + + Ethernet Collision Input + + + Ethernet Receive Data Input + + + Ethernet Receive Error Input + + + Ethernet Receive Clock Input + + + Ethernet Carrier Sense Input + + + Ethernet Receive Data Valid + + + Ethernet PHY Reset + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AXI Timer/Counter + Timer counter with AXI interface + + + + + + + + + + + + + + + + + + + + + + + + + + + Capture Trig 0 + + + Capture Trig 1 + + + Generate Out 0 + + + Generate Out 1 + + + Pulse Width Modulation 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AXI BRAM Controller + Attaches BRAM to the AXI + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Block RAM (BRAM) Block + The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AXI Interrupt Controller + intc core attached to the AXI + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Interrupt Request Output + + + + + + + + + + Interrupt Inputs + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/__xps/xplorer.opt b/Demo/MicroBlaze_Spartan-6_EthernetLite/__xps/xplorer.opt new file mode 100644 index 000000000..f6181b718 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/__xps/xplorer.opt @@ -0,0 +1 @@ + -device xc6slx45tfgg484-3 data/RTOSDemo.ucf 7 0 diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/__xps/xpsxflow.opt b/Demo/MicroBlaze_Spartan-6_EthernetLite/__xps/xpsxflow.opt new file mode 100644 index 000000000..5cd677422 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/__xps/xpsxflow.opt @@ -0,0 +1 @@ + -device xc6slx45tfgg484-3 data/RTOSDemo.ucf 0 diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/data/RTOSDemo.ucf b/Demo/MicroBlaze_Spartan-6_EthernetLite/data/RTOSDemo.ucf new file mode 100644 index 000000000..681ad6274 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/data/RTOSDemo.ucf @@ -0,0 +1,41 @@ +# +# pin constraints +# +NET CLK_N LOC = "K22" | DIFF_TERM = "TRUE" | IOSTANDARD = "LVDS_25"; +NET CLK_P LOC = "K21" | DIFF_TERM = "TRUE" | IOSTANDARD = "LVDS_25"; +NET Ethernet_Lite_COL LOC = "M16" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_CRS LOC = "N15" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_MDC LOC = "R19" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_MDIO LOC = "V20" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_PHY_RST_N LOC = "J22" | IOSTANDARD = "LVCMOS25" | TIG; +NET Ethernet_Lite_RXD[0] LOC = "P19" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_RXD[1] LOC = "Y22" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_RXD[2] LOC = "Y21" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_RXD[3] LOC = "W22" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_RX_CLK LOC = "P20" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_RX_DV LOC = "T22" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_RX_ER LOC = "U20" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_TXD[0] LOC = "U10" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_TXD[1] LOC = "T10" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_TXD[2] LOC = "AB8" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_TXD[3] LOC = "AA8" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_TX_CLK LOC = "L20" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_TX_EN LOC = "T8" | IOSTANDARD = "LVCMOS25"; +NET LEDs_4Bits_TRI_O[0] LOC = "D17" | IOSTANDARD = "LVCMOS25"; +NET LEDs_4Bits_TRI_O[1] LOC = "AB4" | IOSTANDARD = "LVCMOS25"; +NET LEDs_4Bits_TRI_O[2] LOC = "D21" | IOSTANDARD = "LVCMOS25"; +NET LEDs_4Bits_TRI_O[3] LOC = "W15" | IOSTANDARD = "LVCMOS25"; +NET Push_Buttons_4Bits_TRI_I[0] LOC = "F3" | IOSTANDARD = "LVCMOS25"; +NET Push_Buttons_4Bits_TRI_I[1] LOC = "G6" | IOSTANDARD = "LVCMOS25"; +NET Push_Buttons_4Bits_TRI_I[2] LOC = "F5" | IOSTANDARD = "LVCMOS25"; +NET Push_Buttons_4Bits_TRI_I[3] LOC = "C1" | IOSTANDARD = "LVCMOS25"; +NET RESET LOC = "H8" | IOSTANDARD = "LVCMOS15" | TIG; +NET RS232_Uart_1_sin LOC = "H17" | IOSTANDARD = "LVCMOS25"; +NET RS232_Uart_1_sout LOC = "B21" | IOSTANDARD = "LVCMOS25"; +# +# additional constraints +# + +NET "CLK" TNM_NET = sys_clk_pin; +TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 200000 kHz; + diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/etc/RTOSDemo.filters b/Demo/MicroBlaze_Spartan-6_EthernetLite/etc/RTOSDemo.filters new file mode 100644 index 000000000..79ac1a59b --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/etc/RTOSDemo.filters @@ -0,0 +1,159 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/etc/RTOSDemo.gui b/Demo/MicroBlaze_Spartan-6_EthernetLite/etc/RTOSDemo.gui new file mode 100644 index 000000000..66d593ffc --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/etc/RTOSDemo.gui @@ -0,0 +1,223 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/etc/bitgen.ut b/Demo/MicroBlaze_Spartan-6_EthernetLite/etc/bitgen.ut new file mode 100644 index 000000000..bca21c81b --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/etc/bitgen.ut @@ -0,0 +1,3 @@ +-g TdoPin:PULLNONE +-g StartUpClk:JTAGCLK +#add other options here. diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/etc/download.cmd b/Demo/MicroBlaze_Spartan-6_EthernetLite/etc/download.cmd new file mode 100644 index 000000000..da4d7717e --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/etc/download.cmd @@ -0,0 +1,6 @@ +setMode -bscan +setCable -p auto +identify +assignfile -p 2 -file implementation/download.bit +program -p 2 +quit diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/etc/fast_runtime.opt b/Demo/MicroBlaze_Spartan-6_EthernetLite/etc/fast_runtime.opt new file mode 100644 index 000000000..994a6d2f8 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/etc/fast_runtime.opt @@ -0,0 +1,84 @@ +FLOWTYPE = FPGA; +############################################################### +## Filename: fast_runtime.opt +## +## Option File For Xilinx FPGA Implementation Flow for Fast +## Runtime. +## +## Version: 4.1.1 +############################################################### +# +# Options for Translator +# +# Type "ngdbuild -h" for a detailed list of ngdbuild command line options +# +Program ngdbuild +-p ; # Partname to use - picked from xflow commandline +-nt timestamp; # NGO File generation. Regenerate only when + # source netlist is newer than existing + # NGO file (default) +-bm .bmm # Block RAM memory map file +; # User design - pick from xflow command line +-uc .ucf; # ucf constraints +.ngd; # Name of NGD file. Filebase same as design filebase +End Program ngdbuild + +# +# Options for Mapper +# +# Type "map -h " for a detailed list of map command line options +# +Program map +-o _map.ncd; # Output Mapped ncd file +-w; # Overwrite output files. +-pr b; # Pack internal FF/latches into IOBs +#-fp .mfp; # Floorplan file +-ol high; +-timing; +-detail; +.ngd; # Input NGD file +.pcf; # Physical constraints file +END Program map + +# +# Options for Post Map Trace +# +# Type "trce -h" for a detailed list of trce command line options +# +Program post_map_trce +-e 3; # Produce error report limited to 3 items per constraint +#-o _map.twr; # Output trace report file +-xml _map.twx; # Output XML version of the timing report +#-tsi _map.tsi; # Produce Timing Specification Interaction report +_map.ncd; # Input mapped ncd +.pcf; # Physical constraints file +END Program post_map_trce + +# +# Options for Place and Route +# +# Type "par -h" for a detailed list of par command line options +# +Program par +-w; # Overwrite existing placed and routed ncd +-ol high; # Overall effort level +_map.ncd; # Input mapped NCD file +.ncd; # Output placed and routed NCD +.pcf; # Input physical constraints file +END Program par + +# +# Options for Post Par Trace +# +# Type "trce -h" for a detailed list of trce command line options +# +Program post_par_trce +-e 3; # Produce error report limited to 3 items per constraint +#-o .twr; # Output trace report file +-xml .twx; # Output XML version of the timing report +#-tsi .tsi; # Produce Timing Specification Interaction report +.ncd; # Input placed and routed ncd +.pcf; # Physical constraints file +END Program post_par_trce + + diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/implementation/RTOSDemo_summary.html b/Demo/MicroBlaze_Spartan-6_EthernetLite/implementation/RTOSDemo_summary.html new file mode 100644 index 000000000..60d29c321 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/implementation/RTOSDemo_summary.html @@ -0,0 +1,534 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + +
Project Status (05/30/2011 - 21:01:52)
Project File:RTOSDemo.xmpImplementation State:Programming File Generated
Module Name:RTOSDemo
  • Errors:
 +No Errors
Product Version:EDK 13.1
  • Warnings:
130 Warnings (0 new)
+ + + + 
+ + + + + + + + +
XPS Reports [-]
Report NameGeneratedErrorsWarningsInfos
Platgen Log FileMon 30. May 20:53:24 201108 Warnings (8 new)28 Infos (25 new)
Libgen Log File    
Simgen Log File    
BitInit Log File    
System Log FileMon 30. May 21:01:50 2011   
+ 
+ + + + + + + + + + + + + + + + + + + + + + + +
XPS Synthesis Summary (estimated values) [-]
ReportGeneratedFlip Flops UsedLUTs UsedBRAMS UsedErrors
RTOSDemoMon 30. May 20:53:55 201177017505480
clock_generator_0_wrapperMon 30. May 20:53:21 2011   0
microblaze_0_intc_wrapperMon 30. May 19:38:32 20117288 0
axi_bram_ctrl_0_bram_block_wrapperMon 30. May 19:38:24 2011  320
axi_bram_ctrl_0_wrapperMon 30. May 19:38:16 2011406619 0
axi_timer_0_wrapperMon 30. May 19:38:03 2011260272 0
ethernet_lite_wrapperMon 30. May 19:37:52 201146163920
ethernet_lite_wrapper_fifo_generator_v8_1_fifo_generator_v8_1_xst_1Mon 30. May 19:37:36 20117144 0
push_buttons_4bits_wrapperMon 30. May 19:35:44 20117285 0
leds_4bits_wrapperMon 30. May 19:35:34 20113341 0
rs232_uart_1_wrapperMon 30. May 19:35:24 201184102 0
debug_module_wrapperMon 30. May 19:35:15 2011131142 0
proc_sys_reset_0_wrapperMon 30. May 19:35:01 20116955 0
microblaze_0_bram_block_wrapperMon 30. May 19:34:55 2011  40
microblaze_0_d_bram_ctrl_wrapperMon 30. May 19:34:50 201126 0
microblaze_0_i_bram_ctrl_wrapperMon 30. May 19:34:45 201126 0
microblaze_0_dlmb_wrapperMon 30. May 19:34:39 201111 0
microblaze_0_ilmb_wrapperMon 30. May 19:34:35 201111 0
microblaze_0_wrapperMon 30. May 19:34:30 201119892776100
axi4lite_0_wrapperMon 30. May 19:33:39 201127201760 0
axi4_0_wrapperMon 30. May 19:33:14 20111256824 0
+ 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Device Utilization Summary (actual values) [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers5,49154,57610% 
    Number used as Flip Flops5,482   
    Number used as Latches0   
    Number used as Latch-thrus0   
    Number used as AND/OR logics9   
Number of Slice LUTs5,42027,28819% 
    Number used as logic4,95127,28818% 
        Number using O6 output only3,573   
        Number using O5 output only99   
        Number using O5 and O61,279   
        Number used as ROM0   
    Number used as Memory2426,4083% 
        Number used as Dual Port RAM96   
            Number using O6 output only4   
            Number using O5 output only1   
            Number using O5 and O691   
        Number used as Single Port RAM4   
            Number using O6 output only4   
            Number using O5 output only0   
            Number using O5 and O60   
        Number used as Shift Register142   
            Number using O6 output only48   
            Number using O5 output only1   
            Number using O5 and O693   
    Number used exclusively as route-thrus227   
        Number with same-slice register load217   
        Number with same-slice carry load10   
        Number with other load0   
Number of occupied Slices2,2806,82233% 
Number of LUT Flip Flop pairs used6,801   
    Number with an unused Flip Flop2,0686,80130% 
    Number with an unused LUT1,3816,80120% 
    Number of fully used LUT-FF pairs3,3526,80149% 
    Number of unique control sets364   
    Number of slice register sites lost
        to control set restrictions		1,39654,5762% 
Number of bonded IOBs3029610% 
    Number of LOCed IOBs3030100% 
    IOB Flip Flops18   
Number of RAMB16BWERs4811641% 
Number of RAMB8BWERs02320% 
Number of BUFIO2/BUFIO2_2CLKs1323% 
    Number used as BUFIO2s1   
    Number used as BUFIO2_2CLKs0   
Number of BUFIO2FB/BUFIO2FB_2CLKs0320% 
Number of BUFG/BUFGMUXs31618% 
    Number used as BUFGs3   
    Number used as BUFGMUX0   
Number of DCM/DCM_CLKGENs080% 
Number of ILOGIC2/ISERDES2s103762% 
    Number used as ILOGIC2s10   
    Number used as ISERDES2s0   
Number of IODELAY2/IODRP2/IODRP2_MCBs03760% 
Number of OLOGIC2/OSERDES2s73761% 
    Number used as OLOGIC2s7   
    Number used as OSERDES2s0   
Number of BSCANs1425% 
Number of BUFHs02560% 
Number of BUFPLLs080% 
Number of BUFPLL_MCBs040% 
Number of DSP48A1s85813% 
Number of GTPA1_DUALs020% 
Number of ICAPs010% 
Number of MCBs020% 
Number of PCIE_A1s010% 
Number of PCILOGICSEs020% 
Number of PLL_ADVs1425% 
Number of PMVs010% 
Number of STARTUPs010% 
Number of SUSPEND_SYNCs010% 
Average Fanout of Non-Clock Nets3.93   
+ + + + 
+ + + + + + + + + + + + + + + + + +
Performance Summary [-]
Final Timing Score:0 (Setup: 0, Hold: 0, Component Switching Limit: 0)Pinout Data:Pinout Report
Routing Results: +All Signals Completely RoutedClock Data:Clock Report
Timing Constraints: +All Constraints Met  
+ + + + 
+ + + + + + + + +
Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Translation ReportCurrentMon 30. May 20:54:28 2011051 Warnings (0 new)2 Infos (0 new)
Map ReportCurrentMon 30. May 20:59:03 2011026 Warnings (0 new)842 Infos (0 new)
Place and Route ReportCurrentMon 30. May 21:00:37 2011028 Warnings (0 new)3 Infos (0 new)
Post-PAR Static Timing ReportCurrentMon 30. May 21:01:05 2011003 Infos (0 new)
Bitgen ReportCurrentMon 30. May 21:01:52 2011025 Warnings (0 new)0
+ 
+ + + +
Secondary Reports [-]
Report NameStatusGenerated
WebTalk Log FileCurrentMon 30. May 21:01:52 2011
+ + +
Date Generated: 05/30/2011 - 21:01:52
+ \ No newline at end of file