mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-11-04 11:09:01 +01:00
Fix build error for MSP430 and Cortex A with IAR (#937)
* fix whitespace in asm macros * Revert formatting ARM_CA5_No_GIC and ARM_CA9
This commit is contained in:
Jeff Tenney
GitHub
parent
58f0d36e76
commit
5544c78299
@ -1,158 +1,109 @@
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; /*
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* ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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* ; *
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||||
* ; * SPDX-License-Identifier: MIT
|
||||
* ; *
|
||||
* ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* ; * this software and associated documentation files (the "Software"), to deal in
|
||||
* ; * the Software without restriction, including without limitation the rights to
|
||||
* ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* ; * the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* ; * subject to the following conditions:
|
||||
* ; *
|
||||
* ; * The above copyright notice and this permission notice shall be included in all
|
||||
* ; * copies or substantial portions of the Software.
|
||||
* ; *
|
||||
* ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
* ; *
|
||||
* ; * https://www.FreeRTOS.org
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||||
* ; * https://github.com/FreeRTOS
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* ; *
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* ; */
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;/*
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; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
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; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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; *
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||||
; * SPDX-License-Identifier: MIT
|
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; *
|
||||
; * Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
; * this software and associated documentation files (the "Software"), to deal in
|
||||
; * the Software without restriction, including without limitation the rights to
|
||||
; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
; * the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
; * subject to the following conditions:
|
||||
; *
|
||||
; * The above copyright notice and this permission notice shall be included in all
|
||||
; * copies or substantial portions of the Software.
|
||||
; *
|
||||
; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
; *
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; * https://www.FreeRTOS.org
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; * https://github.com/FreeRTOS
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; *
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; */
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EXTERN vTaskSwitchContext
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EXTERN ulCriticalNesting
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EXTERN pxCurrentTCB
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EXTERN ulPortTaskHasFPUContext
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EXTERN ulAsmAPIPriorityMask
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EXTERN vTaskSwitchContext
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EXTERN ulCriticalNesting
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EXTERN pxCurrentTCB
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EXTERN ulPortTaskHasFPUContext
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EXTERN ulAsmAPIPriorityMask
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portSAVE_CONTEXT macro
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;
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Save the LR and SPSR onto the system mode stack before switching to
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;
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system mode to save the remaining system mode registers
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SRSDB sp !, # SYS_MODE
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CPS # SYS_MODE
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PUSH {
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R0 - R12, R14
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}
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; Save the LR and SPSR onto the system mode stack before switching to
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; system mode to save the remaining system mode registers
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SRSDB sp!, #SYS_MODE
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CPS #SYS_MODE
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PUSH {R0-R12, R14}
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;
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Push the critical nesting count
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LDR R2, = ulCriticalNesting
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LDR R1, [ R2 ]
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PUSH {
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R1
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}
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; Push the critical nesting count
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LDR R2, =ulCriticalNesting
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LDR R1, [R2]
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PUSH {R1}
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;
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Does the task have a floating point context that needs saving ? If
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;
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ulPortTaskHasFPUContext is 0 then no.
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LDR R2, = ulPortTaskHasFPUContext
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LDR R3, [ R2 ]
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CMP R3, # 0
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;
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Save the floating point context,
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if any
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FMRXNE R1, FPSCR
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VPUSHNE {
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D0 - D15
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}
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; Does the task have a floating point context that needs saving? If
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; ulPortTaskHasFPUContext is 0 then no.
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LDR R2, =ulPortTaskHasFPUContext
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LDR R3, [R2]
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CMP R3, #0
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; Save the floating point context, if any
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FMRXNE R1, FPSCR
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VPUSHNE {D0-D15}
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#if configFPU_D32 == 1
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VPUSHNE {
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D16 - D31
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}
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#endif; configFPU_D32
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PUSHNE {
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R1
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}
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VPUSHNE {D16-D31}
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#endif ; configFPU_D32
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PUSHNE {R1}
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;
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Save ulPortTaskHasFPUContext itself
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PUSH {
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R3
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}
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; Save ulPortTaskHasFPUContext itself
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PUSH {R3}
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;
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Save the stack pointer in the TCB
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LDR R0, = pxCurrentTCB
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LDR R1, [ R0 ]
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STR SP, [ R1 ]
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; Save the stack pointer in the TCB
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LDR R0, =pxCurrentTCB
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LDR R1, [R0]
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STR SP, [R1]
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endm
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endm
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; /**********************************************************************/
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portRESTORE_CONTEXT macro
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;
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Set the SP to point to the stack of the task being restored.
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LDR R0, = pxCurrentTCB
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LDR R1, [ R0 ]
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LDR SP, [ R1 ]
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; Set the SP to point to the stack of the task being restored.
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LDR R0, =pxCurrentTCB
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LDR R1, [R0]
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LDR SP, [R1]
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;
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Is there a floating point context to restore ? If the restored
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;
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ulPortTaskHasFPUContext is zero then no.
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LDR R0, = ulPortTaskHasFPUContext
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POP {
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R1
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}
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STR R1, [ R0 ]
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CMP R1, # 0
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;
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Restore the floating point context,
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if any
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POPNE {
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R0
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}
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; Is there a floating point context to restore? If the restored
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; ulPortTaskHasFPUContext is zero then no.
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LDR R0, =ulPortTaskHasFPUContext
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POP {R1}
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STR R1, [R0]
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CMP R1, #0
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; Restore the floating point context, if any
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POPNE {R0}
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#if configFPU_D32 == 1
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VPOPNE {
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D16 - D31
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}
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#endif; configFPU_D32
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VPOPNE {
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D0 - D15
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}
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VMSRNE FPSCR, R0
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VPOPNE {D16-D31}
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#endif ; configFPU_D32
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VPOPNE {D0-D15}
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VMSRNE FPSCR, R0
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;
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Restore the critical section nesting depth
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LDR R0, = ulCriticalNesting
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POP {
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R1
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}
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STR R1, [ R0 ]
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; Restore the critical section nesting depth
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LDR R0, =ulCriticalNesting
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POP {R1}
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STR R1, [R0]
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;
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Restore all system mode registers other than the SP( which is already
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;
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being used )
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POP
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{
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R0 - R12, R14
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}
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; Restore all system mode registers other than the SP (which is already
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; being used)
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POP {R0-R12, R14}
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Return to the task code, loading CPSR on the way.CPSR has the interrupt
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;
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enable bit set appropriately
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; Return to the task code, loading CPSR on the way. CPSR has the interrupt
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; enable bit set appropriately for the task about to execute.
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RFEIA sp!
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for the task about to execute.
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RFEIA sp !
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endm
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endm
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@ -1,160 +1,111 @@
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; /*
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* ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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||||
* ; *
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* ; * SPDX-License-Identifier: MIT
|
||||
* ; *
|
||||
* ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* ; * this software and associated documentation files (the "Software"), to deal in
|
||||
* ; * the Software without restriction, including without limitation the rights to
|
||||
* ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* ; * the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* ; * subject to the following conditions:
|
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* ; *
|
||||
* ; * The above copyright notice and this permission notice shall be included in all
|
||||
* ; * copies or substantial portions of the Software.
|
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* ; *
|
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* ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
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* ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
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* ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
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* ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
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* ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
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* ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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||||
* ; *
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||||
* ; * https://www.FreeRTOS.org
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* ; * https://github.com/FreeRTOS
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* ; *
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* ; */
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;/*
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; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
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; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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; *
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; * SPDX-License-Identifier: MIT
|
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; *
|
||||
; * Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
; * this software and associated documentation files (the "Software"), to deal in
|
||||
; * the Software without restriction, including without limitation the rights to
|
||||
; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
; * the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
; * subject to the following conditions:
|
||||
; *
|
||||
; * The above copyright notice and this permission notice shall be included in all
|
||||
; * copies or substantial portions of the Software.
|
||||
; *
|
||||
; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
; *
|
||||
; * https://www.FreeRTOS.org
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; * https://github.com/FreeRTOS
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; *
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; */
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EXTERN vTaskSwitchContext
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EXTERN ulCriticalNesting
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EXTERN pxCurrentTCB
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EXTERN ulPortTaskHasFPUContext
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EXTERN ulAsmAPIPriorityMask
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EXTERN vTaskSwitchContext
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EXTERN ulCriticalNesting
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EXTERN pxCurrentTCB
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EXTERN ulPortTaskHasFPUContext
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EXTERN ulAsmAPIPriorityMask
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portSAVE_CONTEXT macro
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;
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Save the LR and SPSR onto the system mode stack before switching to
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;
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system mode to save the remaining system mode registers
|
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SRSDB sp !, # SYS_MODE
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CPS # SYS_MODE
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PUSH {
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R0 - R12, R14
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}
|
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; Save the LR and SPSR onto the system mode stack before switching to
|
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; system mode to save the remaining system mode registers
|
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SRSDB sp!, #SYS_MODE
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CPS #SYS_MODE
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PUSH {R0-R12, R14}
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;
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Push the critical nesting count
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LDR R2, = ulCriticalNesting
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LDR R1, [ R2 ]
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PUSH {
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R1
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}
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; Push the critical nesting count
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LDR R2, =ulCriticalNesting
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LDR R1, [R2]
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PUSH {R1}
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;
|
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Does the task have a floating point context that needs saving ? If
|
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;
|
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ulPortTaskHasFPUContext is 0 then no.
|
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LDR R2, = ulPortTaskHasFPUContext
|
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LDR R3, [ R2 ]
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CMP R3, # 0
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; Does the task have a floating point context that needs saving? If
|
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; ulPortTaskHasFPUContext is 0 then no.
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LDR R2, =ulPortTaskHasFPUContext
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LDR R3, [R2]
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CMP R3, #0
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;
|
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Save the floating point context,
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; Save the floating point context, if any
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FMRXNE R1, FPSCR
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VPUSHNE {D0-D15}
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VPUSHNE {D16-D31}
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PUSHNE {R1}
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if any
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FMRXNE R1, FPSCR
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VPUSHNE {
|
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D0 - D15
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}
|
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; Save ulPortTaskHasFPUContext itself
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PUSH {R3}
|
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|
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VPUSHNE {
|
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D16 - D31
|
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}
|
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PUSHNE {
|
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R1
|
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}
|
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; Save the stack pointer in the TCB
|
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LDR R0, =pxCurrentTCB
|
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LDR R1, [R0]
|
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STR SP, [R1]
|
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|
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;
|
||||
Save ulPortTaskHasFPUContext itself
|
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PUSH {
|
||||
R3
|
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}
|
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|
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;
|
||||
Save the stack pointer in the TCB
|
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LDR R0, = pxCurrentTCB
|
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LDR R1, [ R0 ]
|
||||
STR SP, [ R1 ]
|
||||
|
||||
endm
|
||||
endm
|
||||
|
||||
; /**********************************************************************/
|
||||
|
||||
portRESTORE_CONTEXT macro
|
||||
|
||||
;
|
||||
Set the SP to point to the stack of the task being restored.
|
||||
LDR R0, = pxCurrentTCB
|
||||
LDR R1, [ R0 ]
|
||||
LDR SP, [ R1 ]
|
||||
; Set the SP to point to the stack of the task being restored.
|
||||
LDR R0, =pxCurrentTCB
|
||||
LDR R1, [R0]
|
||||
LDR SP, [R1]
|
||||
|
||||
;
|
||||
Is there a floating point context to restore ? If the restored
|
||||
;
|
||||
ulPortTaskHasFPUContext is zero then no.
|
||||
LDR R0, = ulPortTaskHasFPUContext
|
||||
POP {
|
||||
R1
|
||||
}
|
||||
STR R1, [ R0 ]
|
||||
CMP R1, # 0
|
||||
; Is there a floating point context to restore? If the restored
|
||||
; ulPortTaskHasFPUContext is zero then no.
|
||||
LDR R0, =ulPortTaskHasFPUContext
|
||||
POP {R1}
|
||||
STR R1, [R0]
|
||||
CMP R1, #0
|
||||
|
||||
;
|
||||
Restore the floating point context,
|
||||
; Restore the floating point context, if any
|
||||
POPNE {R0}
|
||||
VPOPNE {D16-D31}
|
||||
VPOPNE {D0-D15}
|
||||
VMSRNE FPSCR, R0
|
||||
|
||||
if any
|
||||
POPNE {
|
||||
R0
|
||||
}
|
||||
; Restore the critical section nesting depth
|
||||
LDR R0, =ulCriticalNesting
|
||||
POP {R1}
|
||||
STR R1, [R0]
|
||||
|
||||
VPOPNE {
|
||||
D16 - D31
|
||||
}
|
||||
VPOPNE {
|
||||
D0 - D15
|
||||
}
|
||||
VMSRNE FPSCR, R0
|
||||
; Ensure the priority mask is correct for the critical nesting depth
|
||||
LDR R2, =portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS
|
||||
CMP R1, #0
|
||||
MOVEQ R4, #255
|
||||
LDRNE R4, =( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT )
|
||||
STR R4, [r2]
|
||||
|
||||
;
|
||||
Restore the critical section nesting depth
|
||||
LDR R0, = ulCriticalNesting
|
||||
POP {
|
||||
R1
|
||||
}
|
||||
STR R1, [ R0 ]
|
||||
; Restore all system mode registers other than the SP (which is already
|
||||
; being used)
|
||||
POP {R0-R12, R14}
|
||||
|
||||
;
|
||||
Ensure the priority mask is correct
|
||||
; Return to the task code, loading CPSR on the way.
|
||||
RFEIA sp!
|
||||
|
||||
for the critical nesting depth
|
||||
LDR R2, = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS
|
||||
CMP R1, # 0
|
||||
MOVEQ R4, # 255
|
||||
LDRNE R4, = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT )
|
||||
STR R4, [ r2 ]
|
||||
|
||||
;
|
||||
Restore all system mode registers other than the SP( which is already
|
||||
;
|
||||
being used )
|
||||
POP
|
||||
{
|
||||
R0 - R12, R14
|
||||
}
|
||||
|
||||
Return to the task code, loading CPSR on the way.
|
||||
RFEIA sp !
|
||||
|
||||
endm
|
||||
endm
|
||||
|
||||
@ -31,54 +31,54 @@
|
||||
|
||||
portSAVE_CONTEXT macro
|
||||
|
||||
IMPORT pxCurrentTCB
|
||||
IMPORT usCriticalNesting
|
||||
IMPORT pxCurrentTCB
|
||||
IMPORT usCriticalNesting
|
||||
|
||||
/* Save the remaining registers. */
|
||||
push r4
|
||||
push r5
|
||||
push r6
|
||||
push r7
|
||||
push r8
|
||||
push r9
|
||||
push r10
|
||||
push r11
|
||||
push r12
|
||||
push r13
|
||||
push r14
|
||||
push r15
|
||||
mov.w &usCriticalNesting, r14
|
||||
push r14
|
||||
mov.w &pxCurrentTCB, r12
|
||||
mov.w r1, 0 ( r12 )
|
||||
endm
|
||||
/* Save the remaining registers. */
|
||||
push r4
|
||||
push r5
|
||||
push r6
|
||||
push r7
|
||||
push r8
|
||||
push r9
|
||||
push r10
|
||||
push r11
|
||||
push r12
|
||||
push r13
|
||||
push r14
|
||||
push r15
|
||||
mov.w &usCriticalNesting, r14
|
||||
push r14
|
||||
mov.w &pxCurrentTCB, r12
|
||||
mov.w r1, 0(r12)
|
||||
endm
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
portRESTORE_CONTEXT macro
|
||||
mov.w & pxCurrentTCB, r12
|
||||
mov.w @r12, r1
|
||||
pop r15
|
||||
mov.w r15, &usCriticalNesting
|
||||
pop r15
|
||||
pop r14
|
||||
pop r13
|
||||
pop r12
|
||||
pop r11
|
||||
pop r10
|
||||
pop r9
|
||||
pop r8
|
||||
pop r7
|
||||
pop r6
|
||||
pop r5
|
||||
pop r4
|
||||
mov.w &pxCurrentTCB, r12
|
||||
mov.w @r12, r1
|
||||
pop r15
|
||||
mov.w r15, &usCriticalNesting
|
||||
pop r15
|
||||
pop r14
|
||||
pop r13
|
||||
pop r12
|
||||
pop r11
|
||||
pop r10
|
||||
pop r9
|
||||
pop r8
|
||||
pop r7
|
||||
pop r6
|
||||
pop r5
|
||||
pop r4
|
||||
|
||||
/* The last thing on the stack will be the status register.
|
||||
* Ensure the power down bits are clear ready for the next
|
||||
* time this power down register is popped from the stack. */
|
||||
bic.w # 0xf0, 0 ( SP )
|
||||
/* The last thing on the stack will be the status register.
|
||||
* Ensure the power down bits are clear ready for the next
|
||||
* time this power down register is popped from the stack. */
|
||||
bic.w #0xf0, 0(SP)
|
||||
|
||||
reti
|
||||
endm
|
||||
reti
|
||||
endm
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#endif /* ifndef PORTASM_H */
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user