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Add support for 16 MPU regions to Cortex-M4 MPU ports (#96)
ARMv7-M supports 8 or 16 MPU regions. FreeRTOS Cortex-M4 MPU ports so far assumed 8 regions. This change adds support for 16 MPU regions. The hardware with 16 MPU regions must define configTOTAL_MPU_REGIONS to 16 in their FreeRTOSConfig.h. If left undefined, it defaults to 8 for backward compatibility. Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
This commit is contained in:
Gaurav-Aggarwal-AWS
GitHub
parent
367faab135
commit
7dd6b76011
@ -69,7 +69,7 @@
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#define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) )
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#define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) )
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#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
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#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
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#define portEXPECTED_MPU_TYPE_VALUE ( portTOTAL_NUM_REGIONS << 8UL )
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#define portMPU_ENABLE ( 0x01UL )
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#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
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#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
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@ -360,8 +360,15 @@ static void prvRestoreContextOfFirstTask( void )
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" str r3, [r2] \n"/* Disable MPU. */
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" \n"
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" ldr r2, =0xe000ed9c \n"/* Region Base Address register. */
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" ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers from TCB. */
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" stmia r2!, {r4-r11} \n"/* Write 4 sets of MPU registers. */
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" ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
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" stmia r2, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
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" \n"
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#if ( portTOTAL_NUM_REGIONS == 16 )
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" ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
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" stmia r2, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
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" ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
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" stmia r2, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
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#endif /* portTOTAL_NUM_REGIONS == 16. */
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" \n"
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" ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
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" ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
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@ -577,8 +584,15 @@ void xPortPendSVHandler( void )
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" str r3, [r2] \n"/* Disable MPU. */
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" \n"
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" ldr r2, =0xe000ed9c \n"/* Region Base Address register. */
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" ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers from TCB. */
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" stmia r2!, {r4-r11} \n"/* Write 4 sets of MPU registers. */
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" ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
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" stmia r2, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
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" \n"
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#if ( portTOTAL_NUM_REGIONS == 16 )
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" ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
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" stmia r2, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
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" ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
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" stmia r2, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
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#endif /* portTOTAL_NUM_REGIONS == 16. */
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" \n"
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" ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
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" ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
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@ -674,6 +688,12 @@ static void prvSetupMPU( void )
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extern uint32_t __privileged_data_end__[];
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#endif /* if defined( __ARMCC_VERSION ) */
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/* The only permitted number of regions are 8 or 16. */
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configASSERT( ( portTOTAL_NUM_REGIONS == 8 ) || ( portTOTAL_NUM_REGIONS == 16 ) );
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/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
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configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
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/* Check the expected MPU is present. */
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if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
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{
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@ -81,15 +81,21 @@
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#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
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#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
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/* MPU settings that can be overriden in FreeRTOSConfig.h. */
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#ifndef configTOTAL_MPU_REGIONS
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/* Define to 8 for backward compatibility. */
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#define configTOTAL_MPU_REGIONS ( 8UL )
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#endif
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#define portUNPRIVILEGED_FLASH_REGION ( 0UL )
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#define portPRIVILEGED_FLASH_REGION ( 1UL )
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#define portPRIVILEGED_RAM_REGION ( 2UL )
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#define portGENERAL_PERIPHERALS_REGION ( 3UL )
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#define portSTACK_REGION ( 4UL )
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#define portFIRST_CONFIGURABLE_REGION ( 5UL )
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#define portLAST_CONFIGURABLE_REGION ( 7UL )
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#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
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#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
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#define portTOTAL_NUM_REGIONS ( configTOTAL_MPU_REGIONS )
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#define portNUM_CONFIGURABLE_REGIONS ( portTOTAL_NUM_REGIONS - portFIRST_CONFIGURABLE_REGION )
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#define portLAST_CONFIGURABLE_REGION ( portTOTAL_NUM_REGIONS - 1 )
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#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )
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@ -76,7 +76,7 @@
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#define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) )
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#define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) )
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#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
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#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
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#define portEXPECTED_MPU_TYPE_VALUE ( portTOTAL_NUM_REGIONS << 8UL )
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#define portMPU_ENABLE ( 0x01UL )
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#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
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#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
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@ -527,6 +527,12 @@ static void prvSetupMPU( void )
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extern uint32_t __privileged_data_start__[];
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extern uint32_t __privileged_data_end__[];
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/* The only permitted number of regions are 8 or 16. */
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configASSERT( ( portTOTAL_NUM_REGIONS == 8 ) || ( portTOTAL_NUM_REGIONS == 16 ) );
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/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
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configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
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/* Check the expected MPU is present. */
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if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
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{
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@ -91,10 +91,23 @@ xPortPendSVHandler:
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/* Region Base Address register. */
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ldr r2, =0xe000ed9c
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/* Read 4 sets of MPU registers. */
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/* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
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ldmia r1!, {r4-r11}
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/* Write 4 sets of MPU registers. */
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stmia r2!, {r4-r11}
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/* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
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stmia r2, {r4-r11}
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#ifdef configTOTAL_MPU_REGIONS
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#if ( configTOTAL_MPU_REGIONS == 16 )
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/* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
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ldmia r1!, {r4-r11}
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/* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
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stmia r2, {r4-r11}
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/* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
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ldmia r1!, {r4-r11}
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/* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
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stmia r2, {r4-r11}
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#endif /* configTOTAL_MPU_REGIONS == 16. */
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#endif /* configTOTAL_MPU_REGIONS */
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ldr r2, =0xe000ed94 /* MPU_CTRL register. */
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ldr r3, [r2] /* Read the value of MPU_CTRL. */
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@ -178,10 +191,23 @@ vPortRestoreContextOfFirstTask:
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/* Region Base Address register. */
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ldr r2, =0xe000ed9c
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/* Read 4 sets of MPU registers. */
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/* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
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ldmia r1!, {r4-r11}
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/* Write 4 sets of MPU registers. */
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stmia r2!, {r4-r11}
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/* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
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stmia r2, {r4-r11}
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#ifdef configTOTAL_MPU_REGIONS
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#if ( configTOTAL_MPU_REGIONS == 16 )
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/* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
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ldmia r1!, {r4-r11}
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/* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
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stmia r2, {r4-r11}
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/* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
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ldmia r1!, {r4-r11}
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/* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
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stmia r2, {r4-r11}
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#endif /* configTOTAL_MPU_REGIONS == 16. */
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#endif /* configTOTAL_MPU_REGIONS */
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ldr r2, =0xe000ed94 /* MPU_CTRL register. */
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ldr r3, [r2] /* Read the value of MPU_CTRL. */
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@ -84,15 +84,21 @@
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#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
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#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
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/* MPU settings that can be overriden in FreeRTOSConfig.h. */
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#ifndef configTOTAL_MPU_REGIONS
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/* Define to 8 for backward compatibility. */
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#define configTOTAL_MPU_REGIONS ( 8UL )
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#endif
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#define portUNPRIVILEGED_FLASH_REGION ( 0UL )
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#define portPRIVILEGED_FLASH_REGION ( 1UL )
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#define portPRIVILEGED_RAM_REGION ( 2UL )
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#define portGENERAL_PERIPHERALS_REGION ( 3UL )
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#define portSTACK_REGION ( 4UL )
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#define portFIRST_CONFIGURABLE_REGION ( 5UL )
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#define portLAST_CONFIGURABLE_REGION ( 7UL )
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#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
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#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
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#define portTOTAL_NUM_REGIONS ( configTOTAL_MPU_REGIONS )
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#define portNUM_CONFIGURABLE_REGIONS ( portTOTAL_NUM_REGIONS - portFIRST_CONFIGURABLE_REGION )
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#define portLAST_CONFIGURABLE_REGION ( portTOTAL_NUM_REGIONS - 1UL )
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#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, r0, #1 \n msr control, r0 " ::: "r0", "memory" )
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@ -58,7 +58,7 @@
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#define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) )
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#define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) )
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#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
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#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
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#define portEXPECTED_MPU_TYPE_VALUE ( portTOTAL_NUM_REGIONS << 8UL )
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#define portMPU_ENABLE ( 0x01UL )
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#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
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#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
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@ -310,7 +310,7 @@ __asm void vPortSVCHandler( void )
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{
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extern prvSVCHandler
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PRESERVE8
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PRESERVE8
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/* Assumes psp was in use. */
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#ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
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@ -321,6 +321,7 @@ __asm void vPortSVCHandler( void )
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#else
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mrs r0, psp
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#endif
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b prvSVCHandler
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}
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/*-----------------------------------------------------------*/
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@ -329,44 +330,45 @@ __asm void prvRestoreContextOfFirstTask( void )
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{
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PRESERVE8
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ldr r0, = 0xE000ED08 /* Use the NVIC offset register to locate the stack. */
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ldr r0, [ r0 ]
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ldr r0, = 0xE000ED08 /* Use the NVIC offset register to locate the stack. */
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ldr r0, [ r0 ]
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msr msp, r0 /* Set the msp back to the start of the stack. */
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ldr r3, = pxCurrentTCB /* Restore the context. */
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ldr r1, [ r3 ]
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ldr r0, [ r1 ] /* The first item in the TCB is the task top of stack. */
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add r1, r1, # 4 /* Move onto the second item in the TCB... */
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ldr r0, [ r0 ]
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msr msp, r0 /* Set the msp back to the start of the stack. */
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ldr r3, = pxCurrentTCB /* Restore the context. */
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ldr r1, [ r3 ]
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ldr r0, [ r1 ] /* The first item in the TCB is the task top of stack. */
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add r1, r1, # 4 /* Move onto the second item in the TCB... */
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dmb /* Complete outstanding transfers before disabling MPU. */
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ldr r2, = 0xe000ed94 /* MPU_CTRL register. */
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ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
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bic r3, r3, # 1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
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str r3, [ r2 ] /* Disable MPU. */
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dmb /* Complete outstanding transfers before disabling MPU. */
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ldr r2, = 0xe000ed94 /* MPU_CTRL register. */
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ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
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bic r3, r3, # 1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
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str r3, [ r2 ] /* Disable MPU. */
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ldr r2, = 0xe000ed9c /* Region Base Address register. */
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ldmia r1 !, {
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r4 - r11
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} /* Read 4 sets of MPU registers. */
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stmia r2 !, {
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r4 - r11
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} /* Write 4 sets of MPU registers. */
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ldr r2, = 0xe000ed9c /* Region Base Address register. */
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ldmia r1!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
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stmia r2, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
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ldr r2, = 0xe000ed94 /* MPU_CTRL register. */
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ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
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orr r3, r3, # 1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
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str r3, [ r2 ] /* Enable MPU. */
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dsb /* Force memory writes before continuing. */
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#if ( portTOTAL_NUM_REGIONS == 16 )
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ldmia r1!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
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stmia r2, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
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ldmia r1!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
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stmia r2, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
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#endif /* portTOTAL_NUM_REGIONS == 16. */
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ldmia r0 !, {
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r3 - r11, r14
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} /* Pop the registers that are not automatically saved on exception entry. */
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ldr r2, = 0xe000ed94 /* MPU_CTRL register. */
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ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
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orr r3, r3, # 1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
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str r3, [ r2 ] /* Enable MPU. */
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dsb /* Force memory writes before continuing. */
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ldmia r0!, {r3-r11, r14} /* Pop the registers that are not automatically saved on exception entry. */
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msr control, r3
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msr psp, r0 /* Restore the task stack pointer. */
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msr psp, r0 /* Restore the task stack pointer. */
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mov r0, # 0
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msr basepri, r0
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bx r14
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nop
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nop
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}
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/*-----------------------------------------------------------*/
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@ -478,7 +480,7 @@ __asm void prvStartFirstTask( void )
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/* Use the NVIC offset register to locate the stack. */
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ldr r0, = 0xE000ED08
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ldr r0, [ r0 ]
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ldr r0, [ r0 ]
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ldr r0, [ r0 ]
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/* Set the msp back to the start of the stack. */
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msr msp, r0
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@ -496,7 +498,7 @@ __asm void prvStartFirstTask( void )
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isb
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svc portSVC_START_SCHEDULER /* System call to start first task. */
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nop
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nop
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nop
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}
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void vPortEndScheduler( void )
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@ -544,24 +546,18 @@ __asm void xPortPendSVHandler( void )
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mrs r0, psp
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ldr r3, = pxCurrentTCB /* Get the location of the current TCB. */
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ldr r2, [ r3 ]
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ldr r3, = pxCurrentTCB /* Get the location of the current TCB. */
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ldr r2, [ r3 ]
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tst r14, # 0x10 /* Is the task using the FPU context? If so, push high vfp registers. */
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tst r14, # 0x10 /* Is the task using the FPU context? If so, push high vfp registers. */
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it eq
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vstmdbeq r0 !, {
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s16 - s31
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}
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vstmdbeq r0!, {s16-s31}
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mrs r1, control
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stmdb r0 !, {
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r1, r4 - r11, r14
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} /* Save the remaining registers. */
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str r0, [ r2 ] /* Save the new top of stack into the first member of the TCB. */
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stmdb r0!, {r1, r4-r11, r14} /* Save the remaining registers. */
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str r0, [ r2 ] /* Save the new top of stack into the first member of the TCB. */
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stmdb sp !, {
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r0, r3
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}
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stmdb sp!, {r0, r3}
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mov r0, # configMAX_SYSCALL_INTERRUPT_PRIORITY
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msr basepri, r0
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dsb
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||||
@ -569,48 +565,45 @@ __asm void xPortPendSVHandler( void )
|
||||
bl vTaskSwitchContext
|
||||
mov r0, # 0
|
||||
msr basepri, r0
|
||||
ldmia sp !, {
|
||||
r0, r3
|
||||
}
|
||||
ldmia sp!, {r0, r3}
|
||||
/* Restore the context. */
|
||||
ldr r1, [ r3 ]
|
||||
ldr r0, [ r1 ] /* The first item in the TCB is the task top of stack. */
|
||||
add r1, r1, # 4 /* Move onto the second item in the TCB... */
|
||||
ldr r0, [ r1 ] /* The first item in the TCB is the task top of stack. */
|
||||
add r1, r1, # 4 /* Move onto the second item in the TCB... */
|
||||
|
||||
dmb /* Complete outstanding transfers before disabling MPU. */
|
||||
ldr r2, = 0xe000ed94 /* MPU_CTRL register. */
|
||||
ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
|
||||
bic r3, r3, # 1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
|
||||
str r3, [ r2 ] /* Disable MPU. */
|
||||
dmb /* Complete outstanding transfers before disabling MPU. */
|
||||
ldr r2, = 0xe000ed94 /* MPU_CTRL register. */
|
||||
ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
|
||||
bic r3, r3, # 1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
|
||||
str r3, [ r2 ] /* Disable MPU. */
|
||||
|
||||
ldr r2, = 0xe000ed9c /* Region Base Address register. */
|
||||
ldmia r1 !, {
|
||||
r4 - r11
|
||||
} /* Read 4 sets of MPU registers. */
|
||||
stmia r2 !, {
|
||||
r4 - r11
|
||||
} /* Write 4 sets of MPU registers. */
|
||||
ldr r2, = 0xe000ed9c /* Region Base Address register. */
|
||||
ldmia r1!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
|
||||
stmia r2, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
|
||||
|
||||
ldr r2, = 0xe000ed94 /* MPU_CTRL register. */
|
||||
ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
|
||||
orr r3, r3, # 1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
|
||||
str r3, [ r2 ] /* Enable MPU. */
|
||||
dsb /* Force memory writes before continuing. */
|
||||
#if ( portTOTAL_NUM_REGIONS == 16 )
|
||||
ldmia r1!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
|
||||
stmia r2, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
|
||||
ldmia r1!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
|
||||
stmia r2, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
|
||||
#endif /* portTOTAL_NUM_REGIONS == 16. */
|
||||
|
||||
ldmia r0 !, {
|
||||
r3 - r11, r14
|
||||
} /* Pop the registers that are not automatically saved on exception entry. */
|
||||
ldr r2, = 0xe000ed94 /* MPU_CTRL register. */
|
||||
ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
|
||||
orr r3, r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
|
||||
str r3, [ r2 ] /* Enable MPU. */
|
||||
dsb /* Force memory writes before continuing. */
|
||||
|
||||
ldmia r0!, {r3-r11, r14} /* Pop the registers that are not automatically saved on exception entry. */
|
||||
msr control, r3
|
||||
|
||||
tst r14, # 0x10 /* Is the task using the FPU context? If so, pop the high vfp registers too. */
|
||||
tst r14, # 0x10 /* Is the task using the FPU context? If so, pop the high vfp registers too. */
|
||||
it eq
|
||||
vldmiaeq r0 !, {
|
||||
s16 - s31
|
||||
}
|
||||
vldmiaeq r0!, {s16-s31}
|
||||
|
||||
msr psp, r0
|
||||
bx r14
|
||||
nop
|
||||
nop
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
@ -663,7 +656,7 @@ __asm void vPortEnableVFP( void )
|
||||
PRESERVE8
|
||||
|
||||
ldr.w r0, = 0xE000ED88 /* The FPU enable bits are in the CPACR. */
|
||||
ldr r1, [ r0 ]
|
||||
ldr r1, [ r0 ]
|
||||
|
||||
orr r1, r1, # ( 0xf << 20 ) /* Enable CP10 and CP11 coprocessors, then save back. */
|
||||
str r1, [ r0 ]
|
||||
@ -682,6 +675,12 @@ static void prvSetupMPU( void )
|
||||
extern uint32_t __privileged_data_start__;
|
||||
extern uint32_t __privileged_data_end__;
|
||||
|
||||
/* The only permitted number of regions are 8 or 16. */
|
||||
configASSERT( ( portTOTAL_NUM_REGIONS == 8 ) || ( portTOTAL_NUM_REGIONS == 16 ) );
|
||||
|
||||
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
|
||||
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
|
||||
|
||||
/* Check the expected MPU is present. */
|
||||
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
|
||||
{
|
||||
|
||||
@ -81,15 +81,21 @@
|
||||
#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
|
||||
#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
|
||||
|
||||
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
|
||||
#ifndef configTOTAL_MPU_REGIONS
|
||||
/* Define to 8 for backward compatibility. */
|
||||
#define configTOTAL_MPU_REGIONS ( 8UL )
|
||||
#endif
|
||||
|
||||
#define portUNPRIVILEGED_FLASH_REGION ( 0UL )
|
||||
#define portPRIVILEGED_FLASH_REGION ( 1UL )
|
||||
#define portPRIVILEGED_RAM_REGION ( 2UL )
|
||||
#define portGENERAL_PERIPHERALS_REGION ( 3UL )
|
||||
#define portSTACK_REGION ( 4UL )
|
||||
#define portFIRST_CONFIGURABLE_REGION ( 5UL )
|
||||
#define portLAST_CONFIGURABLE_REGION ( 7UL )
|
||||
#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
|
||||
#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
|
||||
#define portTOTAL_NUM_REGIONS ( configTOTAL_MPU_REGIONS )
|
||||
#define portNUM_CONFIGURABLE_REGIONS ( portTOTAL_NUM_REGIONS - portFIRST_CONFIGURABLE_REGION )
|
||||
#define portLAST_CONFIGURABLE_REGION ( portTOTAL_NUM_REGIONS - 1 )
|
||||
|
||||
void vPortSwitchToUserMode( void );
|
||||
#define portSWITCH_TO_USER_MODE() vPortSwitchToUserMode()
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user