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Added a rough pico support. Remove rtos_prints from task.c

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This commit is contained in:
Joseph Julicher 2021-03-16 16:06:23 -07:00
parent 8ab776cc5e
commit ddf9007606
16 changed files with 2824 additions and 23 deletions
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CMakeLists.txt Normal file
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cmake_minimum_required(VERSION 3.12)
add_library(FreeRTOS list.c queue.c tasks.c timers.c event_groups.c)
include_directories(AFTER include)

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portable/ThirdParty/GCC/rpi_pico/CMakeLists.txt vendored Normal file
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cmake_minimum_required(VERSION 3.12)
add_library(FreeRTOS_port port.c)
include_directories(AFTER ../../../include)

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Compiler: /usr/local/bin/arm-none-eabi-c++
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GNU ld (GNU Tools for Arm Embedded Processors 9-2019-q4-major) 2.33.1.20191025/usr/local/Cellar/arm-none-eabi-gcc/9-2019-q4-major/gcc/bin/../lib/gcc/arm-none-eabi/9.2.1/../../../../arm-none-eabi/bin/ld: warning: cannot find entry symbol arch_paths_first; defaulting to 0000000000008018
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collect2: error: ld returned 1 exit status
ninja: build stopped: subcommand failed.
Determining if the C compiler works failed with the following output:
Change Dir: /Users/jjulich/Documents/working/Lab-Project-FreeRTOS-SMP/FreeRTOS/Source/portable/ThirdParty/GCC/rpi_pico/build/CMakeFiles/CMakeTmp
Run Build Command(s):/usr/local/bin/ninja cmTC_7f185 && [1/2] Building C object CMakeFiles/cmTC_7f185.dir/testCCompiler.c.o
[2/2] Linking C executable cmTC_7f185
FAILED: cmTC_7f185
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/usr/local/Cellar/arm-none-eabi-gcc/9-2019-q4-major/gcc/bin/../lib/gcc/arm-none-eabi/9.2.1/../../../../arm-none-eabi/bin/ld: warning: cannot find entry symbol arch_paths_first; defaulting to 0000000000008018
/usr/local/Cellar/arm-none-eabi-gcc/9-2019-q4-major/gcc/bin/../lib/gcc/arm-none-eabi/9.2.1/../../../../arm-none-eabi/bin/ld: /usr/local/Cellar/arm-none-eabi-gcc/9-2019-q4-major/gcc/bin/../lib/gcc/arm-none-eabi/9.2.1/../../../../arm-none-eabi/lib/libc.a(lib_a-exit.o): in function `exit':
exit.c:(.text.exit+0x2c): undefined reference to `_exit'
collect2: error: ld returned 1 exit status
ninja: build stopped: subcommand failed.
Compiling the C compiler identification source file "CMakeCCompilerId.c" failed.
Compiler: /usr/local/bin/arm-none-eabi-gcc-9.2.1
Build flags:
Id flags:
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1
/usr/local/Cellar/arm-none-eabi-gcc/9-2019-q4-major/gcc/bin/../lib/gcc/arm-none-eabi/9.2.1/../../../../arm-none-eabi/bin/ld: /usr/local/Cellar/arm-none-eabi-gcc/9-2019-q4-major/gcc/bin/../lib/gcc/arm-none-eabi/9.2.1/../../../../arm-none-eabi/lib/libc.a(lib_a-exit.o): in function `exit':
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Compiler: /usr/local/bin/arm-none-eabi-c++
Build flags:
Id flags:
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GNU ld (GNU Tools for Arm Embedded Processors 9-2019-q4-major) 2.33.1.20191025/usr/local/Cellar/arm-none-eabi-gcc/9-2019-q4-major/gcc/bin/../lib/gcc/arm-none-eabi/9.2.1/../../../../arm-none-eabi/bin/ld: warning: cannot find entry symbol arch_paths_first; defaulting to 0000000000008018
/usr/local/Cellar/arm-none-eabi-gcc/9-2019-q4-major/gcc/bin/../lib/gcc/arm-none-eabi/9.2.1/../../../../arm-none-eabi/bin/ld: /usr/local/Cellar/arm-none-eabi-gcc/9-2019-q4-major/gcc/bin/../lib/gcc/arm-none-eabi/9.2.1/../../../../arm-none-eabi/lib/libc.a(lib_a-exit.o): in function `exit':
exit.c:(.text.exit+0x2c): undefined reference to `_exit'
collect2: error: ld returned 1 exit status
ninja: build stopped: subcommand failed.
Determining if the C compiler works failed with the following output:
Change Dir: /Users/jjulich/Documents/working/Lab-Project-FreeRTOS-SMP/FreeRTOS/Source/portable/ThirdParty/GCC/rpi_pico/build/CMakeFiles/CMakeTmp
Run Build Command(s):/usr/local/bin/ninja cmTC_b1790 && [1/2] Building C object CMakeFiles/cmTC_b1790.dir/testCCompiler.c.o
[2/2] Linking C executable cmTC_b1790
FAILED: cmTC_b1790
: && /usr/local/bin/arm-none-eabi-gcc-9.2.1 -isysroot /Library/Developer/CommandLineTools/SDKs/MacOSX11.1.sdk -Wl,-search_paths_first -Wl,-headerpad_max_install_names CMakeFiles/cmTC_b1790.dir/testCCompiler.c.o -o cmTC_b1790 && :
/usr/local/Cellar/arm-none-eabi-gcc/9-2019-q4-major/gcc/bin/../lib/gcc/arm-none-eabi/9.2.1/../../../../arm-none-eabi/bin/ld: warning: cannot find entry symbol arch_paths_first; defaulting to 0000000000008018
/usr/local/Cellar/arm-none-eabi-gcc/9-2019-q4-major/gcc/bin/../lib/gcc/arm-none-eabi/9.2.1/../../../../arm-none-eabi/bin/ld: /usr/local/Cellar/arm-none-eabi-gcc/9-2019-q4-major/gcc/bin/../lib/gcc/arm-none-eabi/9.2.1/../../../../arm-none-eabi/lib/libc.a(lib_a-exit.o): in function `exit':
exit.c:(.text.exit+0x2c): undefined reference to `_exit'
collect2: error: ld returned 1 exit status
ninja: build stopped: subcommand failed.

53
portable/ThirdParty/GCC/rpi_pico/build/CMakeFiles/CMakeOutput.log vendored Normal file
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@ -0,0 +1,53 @@
The system is: Darwin - 19.6.0 - x86_64
Compiling the C compiler identification source file "CMakeCCompilerId.c" succeeded.
Compiler: /usr/local/bin/arm-none-eabi-gcc-9.2.1
Build flags:
Id flags: -c
The output was:
0
Compilation of the C compiler identification source "CMakeCCompilerId.c" produced "CMakeCCompilerId.o"
The C compiler identification is GNU, found in "/Users/jjulich/Documents/working/Lab-Project-FreeRTOS-SMP/FreeRTOS/Source/portable/ThirdParty/GCC/rpi_pico/build/CMakeFiles/3.19.2/CompilerIdC/CMakeCCompilerId.o"
Compiling the CXX compiler identification source file "CMakeCXXCompilerId.cpp" succeeded.
Compiler: /usr/local/bin/arm-none-eabi-c++
Build flags:
Id flags: -c
The output was:
0
Compilation of the CXX compiler identification source "CMakeCXXCompilerId.cpp" produced "CMakeCXXCompilerId.o"
The CXX compiler identification is GNU, found in "/Users/jjulich/Documents/working/Lab-Project-FreeRTOS-SMP/FreeRTOS/Source/portable/ThirdParty/GCC/rpi_pico/build/CMakeFiles/3.19.2/CompilerIdCXX/CMakeCXXCompilerId.o"
Compiling the C compiler identification source file "CMakeCCompilerId.c" succeeded.
Compiler: /usr/local/bin/arm-none-eabi-gcc-9.2.1
Build flags:
Id flags: -c
The output was:
0
Compilation of the C compiler identification source "CMakeCCompilerId.c" produced "CMakeCCompilerId.o"
The C compiler identification is GNU, found in "/Users/jjulich/Documents/working/Lab-Project-FreeRTOS-SMP/FreeRTOS/Source/portable/ThirdParty/GCC/rpi_pico/build/CMakeFiles/3.19.2/CompilerIdC/CMakeCCompilerId.o"
Compiling the CXX compiler identification source file "CMakeCXXCompilerId.cpp" succeeded.
Compiler: /usr/local/bin/arm-none-eabi-c++
Build flags:
Id flags: -c
The output was:
0
Compilation of the CXX compiler identification source "CMakeCXXCompilerId.cpp" produced "CMakeCXXCompilerId.o"
The CXX compiler identification is GNU, found in "/Users/jjulich/Documents/working/Lab-Project-FreeRTOS-SMP/FreeRTOS/Source/portable/ThirdParty/GCC/rpi_pico/build/CMakeFiles/3.19.2/CompilerIdCXX/CMakeCXXCompilerId.o"

1
portable/ThirdParty/GCC/rpi_pico/build/CMakeFiles/cmake.check_cache vendored Normal file
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# This file is generated by cmake for dependency checking of the CMakeCache.txt file

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#ifndef PICO_SUPPORT_H
#define PICO_SUPPORT_H
/* Constants required to manipulate the SIE. */
#define portSIE_BASE 0xd0000000
#define SIE_OFFSET(a) ( * ( ( volatile uint32_t * ) ( portSIE_BASE + a ) ) )
#define portSIE_CPUID SIE_OFFSET( 0x00 )
#define portSIE_GPIO_IN SIE_OFFSET( 0x04 )
#define portSIE_GPIO_HI_IN SIE_OFFSET( 0x08 )
#define portSIE_GPIO_OUT SIE_OFFSET( 0x10 )
#define portSIE_GPIO_OUT_SET SIE_OFFSET( 0x14 )
#define portSIE_GPIO_OUT_CLR SIE_OFFSET( 0x18 )
#define portSIE_GPIO_OUT_XOR SIE_OFFSET( 0x1C )
#define portSIE_GPIO_OE SIE_OFFSET( 0x20 )
#define portSIE_GPIO_OE_SET SIE_OFFSET( 0x24 )
#define portSIE_GPIO_OE_CLR SIE_OFFSET( 0x28 )
#define portSIE_GPIO_OE_XOR SIE_OFFSET( 0x2C )
#define portSIE_GPIO_HI_OUT SIE_OFFSET( 0x30 )
#define portSIE_GPIO_HI_OUT_SET SIE_OFFSET( 0x34 )
#define portSIE_GPIO_HI_OUT_CLR SIE_OFFSET( 0x38 )
#define portSIE_GPIO_HI_OUT_XOR SIE_OFFSET( 0x3C )
#define portSIE_GPIO_HI_OE SIE_OFFSET( 0x40 )
#define portSIE_GPIO_HI_OE_SET SIE_OFFSET( 0x44 )
#define portSIE_GPIO_HI_OE_CLR SIE_OFFSET( 0x48 )
#define portSIE_GPIO_HI_OE_XOR SIE_OFFSET( 0x4C )
#define portSIE_FIFO_ST SIE_OFFSET( 0x50 )
#define portSIE_FIFO_WR SIE_OFFSET( 0x54 )
#define portSIE_FIFO_RD SIE_OFFSET( 0x58 )
#define portSIE_SPINLOCK_ST SIE_OFFSET( 0x5C )
#define portSIE_DIV_UDIVIDEND SIE_OFFSET( 0x60 )
#define portSIE_DIV_UDIVISOR SIE_OFFSET( 0x64 )
#define portSIE_DIV_SDIVIDEND SIE_OFFSET( 0x68 )
#define portSIE_DIV_SDIVISOR SIE_OFFSET( 0x6C )
#define portSIE_DIV_QUOTIENT SIE_OFFSET( 0x70 )
#define portSIE_DIV_REMAINDER SIE_OFFSET( 0x74 )
#define portSIE_DIV_CSR SIE_OFFSET( 0x78 )
#define portSIE_INTERP0_ACCUM0 SIE_OFFSET( 0x80 )
#define portSIE_INTERP0_ACCUM1 SIE_OFFSET( 0x84 )
#define portSIE_INTERP0_BASE0 SIE_OFFSET( 0x88 )
#define portSIE_INTERP0_BASE1 SIE_OFFSET( 0x8C )
#define portSIE_INTERP0_BASE2 SIE_OFFSET( 0x90 )
#define portSIE_INTERP0_POP_LANE0 SIE_OFFSET( 0x94 )
#define portSIE_INTERP0_POP_LANE1 SIE_OFFSET( 0x98 )
#define portSIE_INTERP0_POP_FULL SIE_OFFSET( 0x9C )
#define portSIE_INTERP0_PEEK_LANE0 SIE_OFFSET( 0xA0 )
#define portSIE_INTERP0_PEEK_LANE1 SIE_OFFSET( 0xA4 )
#define portSIE_INTERP0_PEEK_FULL SIE_OFFSET( 0xA8 )
#define portSIE_INTERP0_CTRL_LANE0 SIE_OFFSET( 0xAC )
#define portSIE_INTERP0_CTRL_LANE1 SIE_OFFSET( 0xB0 )
#define portSIE_INTERP0_ACCUM0_ADD SIE_OFFSET( 0xB4 )
#define portSIE_INTERP0_ACCUM1_ADD SIE_OFFSET( 0xB8 )
#define portSIE_INTERP0_BASE_1AND0 SIE_OFFSET( 0xBC )
#define portSIE_INTERP1_ACCUM0 SIE_OFFSET( 0xC0 )
#define portSIE_INTERP1_ACCUM1 SIE_OFFSET( 0xC4 )
#define portSIE_INTERP1_BASE0 SIE_OFFSET( 0xC8 )
#define portSIE_INTERP1_BASE1 SIE_OFFSET( 0xCC )
#define portSIE_INTERP1_BASE2 SIE_OFFSET( 0xD0 )
#define portSIE_INTERP1_POP_LANE0 SIE_OFFSET( 0xD4 )
#define portSIE_INTERP1_POP_LANE1 SIE_OFFSET( 0xD8 )
#define portSIE_INTERP1_POP_FULL SIE_OFFSET( 0xDC )
#define portSIE_INTERP1_PEEK_LANE0 SIE_OFFSET( 0xE0 )
#define portSIE_INTERP1_PEEK_LANE1 SIE_OFFSET( 0xE4 )
#define portSIE_INTERP1_PEEK_FULL SIE_OFFSET( 0xE8 )
#define portSIE_INTERP1_CTRL_LANE0 SIE_OFFSET( 0xEC )
#define portSIE_INTERP1_CTRL_LANE1 SIE_OFFSET( 0xF0 )
#define portSIE_INTERP1_ACCUM0_ADD SIE_OFFSET( 0xF4 )
#define portSIE_INTERP1_ACCUM1_ADD SIE_OFFSET( 0xF8 )
#define portSIE_INTERP1_BASE_1AND0 SIE_OFFSET( 0xFC )
#define portSIE_SPINLOCK0 SIE_OFFSET( 0x100 )
#define portSIE_SPINLOCK1 SIE_OFFSET( 0x104 )
#define portSIE_SPINLOCK2 SIE_OFFSET( 0x108 )
#define portSIE_SPINLOCK3 SIE_OFFSET( 0x10C )
#define portSIE_SPINLOCK4 SIE_OFFSET( 0x110 )
#define portSIE_SPINLOCK5 SIE_OFFSET( 0x114 )
#define portSIE_SPINLOCK6 SIE_OFFSET( 0x118 )
#define portSIE_SPINLOCK7 SIE_OFFSET( 0x11C )
#define portSIE_SPINLOCK8 SIE_OFFSET( 0x120 )
#define portSIE_SPINLOCK9 SIE_OFFSET( 0x124 )
#define portSIE_SPINLOCK10 SIE_OFFSET( 0x128 )
#define portSIE_SPINLOCK11 SIE_OFFSET( 0x12C )
#define portSIE_SPINLOCK12 SIE_OFFSET( 0x130 )
#define portSIE_SPINLOCK13 SIE_OFFSET( 0x134 )
#define portSIE_SPINLOCK14 SIE_OFFSET( 0x138 )
#define portSIE_SPINLOCK15 SIE_OFFSET( 0x13C )
#define portSIE_SPINLOCK16 SIE_OFFSET( 0x140 )
#define portSIE_SPINLOCK17 SIE_OFFSET( 0x144 )
#define portSIE_SPINLOCK18 SIE_OFFSET( 0x148 )
#define portSIE_SPINLOCK19 SIE_OFFSET( 0x14C )
#define portSIE_SPINLOCK20 SIE_OFFSET( 0x150 )
#define portSIE_SPINLOCK21 SIE_OFFSET( 0x154 )
#define portSIE_SPINLOCK22 SIE_OFFSET( 0x158 )
#define portSIE_SPINLOCK23 SIE_OFFSET( 0x15C )
#define portSIE_SPINLOCK24 SIE_OFFSET( 0x160 )
#define portSIE_SPINLOCK25 SIE_OFFSET( 0x164 )
#define portSIE_SPINLOCK26 SIE_OFFSET( 0x168 )
#define portSIE_SPINLOCK27 SIE_OFFSET( 0x16C )
#define portSIE_SPINLOCK28 SIE_OFFSET( 0x170 )
#define portSIE_SPINLOCK29 SIE_OFFSET( 0x174 )
#define portSIE_SPINLOCK30 SIE_OFFSET( 0x178 )
#define portSIE_SPINLOCK31 SIE_OFFSET( 0x17C )
#endif

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/*
* FreeRTOS Kernel V10.4.3
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/*-----------------------------------------------------------
* Implementation of functions defined in portable.h for the ARM CM0 port.
*----------------------------------------------------------*/
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Constants required to manipulate the NVIC. */
#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
/* Constants required to set up the initial stack. */
#define portINITIAL_XPSR ( 0x01000000 )
/* The systick is a 24-bit counter. */
#define portMAX_24_BIT_NUMBER ( 0xffffffUL )
/* A fiddle factor to estimate the number of SysTick counts that would have
* occurred while the SysTick counter is stopped during tickless idle
* calculations. */
#ifndef portMISSED_COUNTS_FACTOR
#define portMISSED_COUNTS_FACTOR ( 45UL )
#endif
/* Let the user override the pre-loading of the initial LR with the address of
* prvTaskExitError() in case it messes up unwinding of the stack in the
* debugger. */
#ifdef configTASK_RETURN_ADDRESS
#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
#else
#define portTASK_RETURN_ADDRESS prvTaskExitError
#endif
/*
* Setup the timer to generate the tick interrupts. The implementation in this
* file is weak to allow application writers to change the timer used to
* generate the tick interrupt.
*/
void vPortSetupTimerInterrupt( void );
/*
* Exception handlers.
*/
void xPortPendSVHandler( void ) __attribute__( ( naked ) );
void xPortSysTickHandler( void );
void vPortSVCHandler( void );
/*
* Start first task is a separate function so it can be tested in isolation.
*/
static void vPortStartFirstTask( void ) __attribute__( ( naked ) );
/*
* Used to catch tasks that attempt to return from their implementing function.
*/
static void prvTaskExitError( void );
/*-----------------------------------------------------------*/
/* Each task maintains its own interrupt status in the critical nesting
* variable. */
static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
/*-----------------------------------------------------------*/
/*
* The number of SysTick increments that make up one tick period.
*/
#if ( configUSE_TICKLESS_IDLE == 1 )
static uint32_t ulTimerCountsForOneTick = 0;
#endif /* configUSE_TICKLESS_IDLE */
/*
* The maximum number of tick periods that can be suppressed is limited by the
* 24 bit resolution of the SysTick timer.
*/
#if ( configUSE_TICKLESS_IDLE == 1 )
static uint32_t xMaximumPossibleSuppressedTicks = 0;
#endif /* configUSE_TICKLESS_IDLE */
/*
* Compensate for the CPU cycles that pass while the SysTick is stopped (low
* power functionality only.
*/
#if ( configUSE_TICKLESS_IDLE == 1 )
static uint32_t ulStoppedTimerCompensation = 0;
#endif /* configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*/
/*
* See header file for description.
*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
{
/* Simulate the stack frame as it would be created by a context switch
* interrupt. */
pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
*pxTopOfStack = portINITIAL_XPSR; /* xPSR */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; /* PC */
pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
pxTopOfStack -= 8; /* R11..R4. */
return pxTopOfStack;
}
/*-----------------------------------------------------------*/
static void prvTaskExitError( void )
{
volatile uint32_t ulDummy = 0UL;
/* A function that implements a task must not exit or attempt to return to
* its caller as there is nothing to return to. If a task wants to exit it
* should instead call vTaskDelete( NULL ).
*
* Artificially force an assert() to be triggered if configASSERT() is
* defined, then stop here so application writers can catch the error. */
configASSERT( uxCriticalNesting == ~0UL );
portDISABLE_INTERRUPTS();
while( ulDummy == 0 )
{
/* This file calls prvTaskExitError() after the scheduler has been
* started to remove a compiler warning about the function being defined
* but never called. ulDummy is used purely to quieten other warnings
* about code appearing after this function is called - making ulDummy
* volatile makes the compiler think the function could return and
* therefore not output an 'unreachable code' warning for code that appears
* after it. */
}
}
/*-----------------------------------------------------------*/
void vPortSVCHandler( void )
{
/* This function is no longer used, but retained for backward
* compatibility. */
}
/*-----------------------------------------------------------*/
void vPortStartFirstTask( void )
{
/* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector
* table offset register that can be used to locate the initial stack value.
* Not all M0 parts have the application vector table at address 0. */
__asm volatile (
" .syntax unified \n"
" ldr r2, pxCurrentTCBConst2 \n"/* Obtain location of pxCurrentTCB. */
" ldr r3, [r2] \n"
" ldr r0, [r3] \n"/* The first item in pxCurrentTCB is the task top of stack. */
" adds r0, #32 \n"/* Discard everything up to r0. */
" msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
" movs r0, #2 \n"/* Switch to the psp stack. */
" msr CONTROL, r0 \n"
" isb \n"
" pop {r0-r5} \n"/* Pop the registers that are saved automatically. */
" mov lr, r5 \n"/* lr is now in r5. */
" pop {r3} \n"/* Return address is now in r3. */
" pop {r2} \n"/* Pop and discard XPSR. */
" cpsie i \n"/* The first task has its context and interrupts can be enabled. */
" bx r3 \n"/* Finally, jump to the user defined task code. */
" \n"
" .align 4 \n"
"pxCurrentTCBConst2: .word pxCurrentTCB "
);
}
/*-----------------------------------------------------------*/
/*
* See header file for description.
*/
BaseType_t xPortStartScheduler( void )
{
/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
/* Start the timer that generates the tick ISR. Interrupts are disabled
* here already. */
vPortSetupTimerInterrupt();
/* Initialise the critical nesting count ready for the first task. */
uxCriticalNesting = 0;
/* Start the first task. */
vPortStartFirstTask();
/* Should never get here as the tasks will now be executing! Call the task
* exit error function to prevent compiler warnings about a static function
* not being called in the case that the application writer overrides this
* functionality by defining configTASK_RETURN_ADDRESS. Call
* vTaskSwitchContext() so link time optimisation does not remove the
* symbol. */
vTaskSwitchContext(0);
prvTaskExitError();
/* Should not get here! */
return 0;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
/* Not implemented in ports where there is nothing to return to.
* Artificially force an assert. */
configASSERT( uxCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
void vPortYield( void )
{
/* Set a PendSV to request a context switch. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
/* Barriers are normally not required but do ensure the code is completely
* within the specified behaviour for the architecture. */
__asm volatile ( "dsb" ::: "memory" );
__asm volatile ( "isb" );
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
portDISABLE_INTERRUPTS();
uxCriticalNesting++;
__asm volatile ( "dsb" ::: "memory" );
__asm volatile ( "isb" );
}
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
configASSERT( uxCriticalNesting );
uxCriticalNesting--;
if( uxCriticalNesting == 0 )
{
portENABLE_INTERRUPTS();
}
}
/*-----------------------------------------------------------*/
uint32_t ulSetInterruptMaskFromISR( void )
{
__asm volatile (
" mrs r0, PRIMASK \n"
" cpsid i \n"
" bx lr "
::: "memory"
);
}
/*-----------------------------------------------------------*/
void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask )
{
__asm volatile (
" msr PRIMASK, r0 \n"
" bx lr "
::: "memory"
);
}
/*-----------------------------------------------------------*/
void xPortPendSVHandler( void )
{
/* This is a naked function. */
__asm volatile
(
" .syntax unified \n"
" mrs r0, psp \n"
" \n"
" ldr r3, pxCurrentTCBConst \n"/* Get the location of the current TCB. */
" ldr r2, [r3] \n"
" \n"
" subs r0, r0, #32 \n"/* Make space for the remaining low registers. */
" str r0, [r2] \n"/* Save the new top of stack. */
" stmia r0!, {r4-r7} \n"/* Store the low registers that are not saved automatically. */
" mov r4, r8 \n"/* Store the high registers. */
" mov r5, r9 \n"
" mov r6, r10 \n"
" mov r7, r11 \n"
" stmia r0!, {r4-r7} \n"
" \n"
" push {r3, r14} \n"
" cpsid i \n"
" bl vTaskSwitchContext \n"
" cpsie i \n"
" pop {r2, r3} \n"/* lr goes in r3. r2 now holds tcb pointer. */
" \n"
" ldr r1, [r2] \n"
" ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */
" adds r0, r0, #16 \n"/* Move to the high registers. */
" ldmia r0!, {r4-r7} \n"/* Pop the high registers. */
" mov r8, r4 \n"
" mov r9, r5 \n"
" mov r10, r6 \n"
" mov r11, r7 \n"
" \n"
" msr psp, r0 \n"/* Remember the new top of stack for the task. */
" \n"
" subs r0, r0, #32 \n"/* Go back for the low registers that are not automatically restored. */
" ldmia r0!, {r4-r7} \n"/* Pop low registers. */
" \n"
" bx r3 \n"
" \n"
" .align 4 \n"
"pxCurrentTCBConst: .word pxCurrentTCB "
);
}
/*-----------------------------------------------------------*/
void xPortSysTickHandler( void )
{
uint32_t ulPreviousMask;
ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
/* Pend a context switch. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
}
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
}
/*-----------------------------------------------------------*/
/*
* Setup the systick timer to generate the tick interrupts at the required
* frequency.
*/
__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
{
/* Calculate the constants required to configure the tick interrupt. */
#if ( configUSE_TICKLESS_IDLE == 1 )
{
ulTimerCountsForOneTick = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR;
}
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and reset the SysTick. */
portNVIC_SYSTICK_CTRL_REG = 0UL;
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
}
/*-----------------------------------------------------------*/
#if ( configUSE_TICKLESS_IDLE == 1 )
__attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
TickType_t xModifiableIdleTime;
/* Make sure the SysTick reload value does not overflow the counter. */
if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
{
xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
}
/* Stop the SysTick momentarily. The time the SysTick is stopped for
* is accounted for as best it can be, but using the tickless mode will
* inevitably result in some tiny drift of the time maintained by the
* kernel with respect to calendar time. */
portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
/* Calculate the reload value required to wait xExpectedIdleTime
* tick periods. -1 is used because this code will execute part way
* through one of the tick periods. */
ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
if( ulReloadValue > ulStoppedTimerCompensation )
{
ulReloadValue -= ulStoppedTimerCompensation;
}
/* Enter a critical section but don't use the taskENTER_CRITICAL()
* method as that will mask interrupts that should exit sleep mode. */
__asm volatile ( "cpsid i" ::: "memory" );
__asm volatile ( "dsb" );
__asm volatile ( "isb" );
/* If a context switch is pending or a task is waiting for the scheduler
* to be unsuspended then abandon the low power entry. */
if( eTaskConfirmSleepModeStatus() == eAbortSleep )
{
/* Restart from whatever is left in the count register to complete
* this tick period. */
portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
/* Restart SysTick. */
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
/* Reset the reload register to the value required for normal tick
* periods. */
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Re-enable interrupts - see comments above the cpsid instruction()
* above. */
__asm volatile ( "cpsie i" ::: "memory" );
}
else
{
/* Set the new reload value. */
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
/* Clear the SysTick count flag and set the count value back to
* zero. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Restart SysTick. */
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
/* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
* set its parameter to 0 to indicate that its implementation contains
* its own wait for interrupt or wait for event instruction, and so wfi
* should not be executed again. However, the original expected idle
* time variable must remain unmodified, so a copy is taken. */
xModifiableIdleTime = xExpectedIdleTime;
configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
if( xModifiableIdleTime > 0 )
{
__asm volatile ( "dsb" ::: "memory" );
__asm volatile ( "wfi" );
__asm volatile ( "isb" );
}
configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
/* Re-enable interrupts to allow the interrupt that brought the MCU
* out of sleep mode to execute immediately. see comments above
* __disable_interrupt() call above. */
__asm volatile ( "cpsie i" ::: "memory" );
__asm volatile ( "dsb" );
__asm volatile ( "isb" );
/* Disable interrupts again because the clock is about to be stopped
* and interrupts that execute while the clock is stopped will increase
* any slippage between the time maintained by the RTOS and calendar
* time. */
__asm volatile ( "cpsid i" ::: "memory" );
__asm volatile ( "dsb" );
__asm volatile ( "isb" );
/* Disable the SysTick clock without reading the
* portNVIC_SYSTICK_CTRL_REG register to ensure the
* portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
* the time the SysTick is stopped for is accounted for as best it can
* be, but using the tickless mode will inevitably result in some tiny
* drift of the time maintained by the kernel with respect to calendar
* time*/
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
/* Determine if the SysTick clock has already counted to zero and
* been set back to the current reload value (the reload back being
* correct for the entire expected idle time) or if the SysTick is yet
* to count to zero (in which case an interrupt other than the SysTick
* must have brought the system out of sleep mode). */
if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
{
uint32_t ulCalculatedLoadValue;
/* The tick interrupt is already pending, and the SysTick count
* reloaded with ulReloadValue. Reset the
* portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
* period. */
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
/* Don't allow a tiny value, or values that have somehow
* underflowed because the post sleep hook did something
* that took too long. */
if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
{
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
}
portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
/* As the pending tick will be processed as soon as this
* function exits, the tick value maintained by the tick is stepped
* forward by one less than the time spent waiting. */
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
}
else
{
/* Something other than the tick interrupt ended the sleep.
* Work out how long the sleep lasted rounded to complete tick
* periods (not the ulReload value which accounted for part
* ticks). */
ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
/* How many complete tick periods passed while the processor
* was waiting? */
ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
/* The reload value is set to whatever fraction of a single tick
* period remains. */
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
}
/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
* again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
* value. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
vTaskStepTick( ulCompleteTickPeriods );
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Exit with interrpts enabled. */
__asm volatile ( "cpsie i" ::: "memory" );
}
}
#endif /* configUSE_TICKLESS_IDLE */

150
portable/ThirdParty/GCC/rpi_pico/portmacro.h vendored Normal file
View File

@ -0,0 +1,150 @@
/*
* FreeRTOS Kernel V10.4.3
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
* 1 tab == 4 spaces!
*/
// TODO Guard this so it only arrives with the PICO
#include "pico_support.h"
#ifndef PORTMACRO_H
#define PORTMACRO_H
#ifdef __cplusplus
extern "C" {
#endif
/*-----------------------------------------------------------
* Port specific definitions.
*
* The settings in this file configure FreeRTOS correctly for the
* given hardware and compiler.
*
* These settings should not be altered.
*-----------------------------------------------------------
*/
/* Type definitions. */
#define portCHAR char
#define portFLOAT float
#define portDOUBLE double
#define portLONG long
#define portSHORT short
#define portSTACK_TYPE uint32_t
#define portBASE_TYPE long
typedef portSTACK_TYPE StackType_t;
typedef long BaseType_t;
typedef unsigned long UBaseType_t;
#if ( configUSE_16_BIT_TICKS == 1 )
typedef uint16_t TickType_t;
#define portMAX_DELAY ( TickType_t ) 0xffff
#else
typedef uint32_t TickType_t;
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
#endif
/*-----------------------------------------------------------*/
/* Architecture specifics. */
#define portSTACK_GROWTH ( -1 )
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
#define portBYTE_ALIGNMENT 8
#define portDONT_DISCARD __attribute__( ( used ) )
// TODO SMP this is in tasks.c & the xmos port
#define portCRITICAL_NESTING_IN_TCB 1
/*-----------------------------------------------------------*/
/* Scheduler utilities. */
extern void vPortYield( void );
#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
#define portYIELD() vPortYield()
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
/* SMP utilities */
#define portGET_CORE_ID() (portSIE_CPUID)
// TODO SMP Implement this
#define portYIELD_CORE(a)
// TODO SMP NEW. Restore the maskable interrupt state to the valued provided.
#define portRESTORE_INTERRUPTS(ulState)
// TODO SMP NEW. Return a true if we are currently in an ISR and false if we are NOT in an ISR.
#define portCHECK_IF_IN_ISR() (pdFALSE)
/*-----------------------------------------------------------*/
/* Critical section management. */
extern void vPortEnterCritical( void );
extern void vPortExitCritical( void );
extern uint32_t ulSetInterruptMaskFromISR( void ) __attribute__( ( naked ) );
extern void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__( ( naked ) );
#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMaskFromISR( x )
// TODO SMP XMOS modified DISABLE_INTERRUPTS to return a value
#define portDISABLE_INTERRUPTS() ({ __asm volatile ( " cpsid i " ::: "memory" ); 0;})
#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
#define portENTER_CRITICAL() vPortEnterCritical()
#define portEXIT_CRITICAL() vPortExitCritical()
/* PICO port will use the HW spinlocks for these */
/* Read Page 32 of the RP2040 datasheet to see how the spinlocks wrok */
/* using SPINLOCK0 for the ISR & SPINLOCK1 for the task */
#define portGET_ISR_LOCK() do{ while(!portSIE_SPINLOCK0); }while(0)
#define portRELEASE_ISR_LOCK() do{ portSIE_SPINLOCK0 = 1; }while(0)
#define portGET_TASK_LOCK() do{ while(!portSIE_SPINLOCK1); }while(0)
#define portRELEASE_TASK_LOCK() do{ portSIE_SPINLOCK1 = 1; }while(0)
/*-----------------------------------------------------------*/
/* Tickless idle/low power functionality. */
#ifndef portSUPPRESS_TICKS_AND_SLEEP
extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
#endif
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
#define portNOP()
#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
#ifdef __cplusplus
}
#endif
#endif /* PORTMACRO_H */

23
tasks.c
View File

@ -894,7 +894,6 @@ static void prvYieldForTask( TCB_t * pxTCB,
#endif #endif
{ {
/* If the task is not being executed by any core swap it in */ /* If the task is not being executed by any core swap it in */
/*rtos_printf("Current priority %d: swap out %s(%d) for %s(%d) on core %d\n", uxCurrentPriority, pxCurrentTCBs[ portGET_CORE_ID() ]->pcTaskName, pxCurrentTCBs[ portGET_CORE_ID() ]->uxPriority, pxTCB->pcTaskName, pxTCB->uxPriority, portGET_CORE_ID()); */
pxCurrentTCBs[ xCoreID ]->xTaskRunState = taskTASK_NOT_RUNNING; pxCurrentTCBs[ xCoreID ]->xTaskRunState = taskTASK_NOT_RUNNING;
#if ( configUSE_CORE_EXCLUSION == 1 ) #if ( configUSE_CORE_EXCLUSION == 1 )
pxPreviousTCB = pxCurrentTCBs[ xCoreID ]; pxPreviousTCB = pxCurrentTCBs[ xCoreID ];
@ -914,7 +913,6 @@ static void prvYieldForTask( TCB_t * pxTCB,
/* The task is already running on this core, mark it as scheduled */ /* The task is already running on this core, mark it as scheduled */
pxTCB->xTaskRunState = ( TaskRunning_t ) xCoreID; pxTCB->xTaskRunState = ( TaskRunning_t ) xCoreID;
xTaskScheduled = pdTRUE; xTaskScheduled = pdTRUE;
/*rtos_printf( "Keeping %s(%d) on core %d\n", pxTCB->pcTaskName, pxTCB->uxPriority, portGET_CORE_ID() ); */
} }
} }
@ -995,7 +993,6 @@ static void prvYieldForTask( TCB_t * pxTCB,
{ {
/* The ready task that was removed from this core is excluded from it. /* The ready task that was removed from this core is excluded from it.
* See if we can schedule it on any of the cores where it is not excluded from. */ * See if we can schedule it on any of the cores where it is not excluded from. */
rtos_printf( "Kicked %s off core %d\n", pxPreviousTCB->pcTaskName, xCoreID );
} }
uxCoreMap &= ( ( 1 << configNUM_CORES ) - 1 ); uxCoreMap &= ( ( 1 << configNUM_CORES ) - 1 );
@ -1024,12 +1021,6 @@ static void prvYieldForTask( TCB_t * pxTCB,
if( taskVALID_CORE_ID( xLowestPriorityCore ) ) if( taskVALID_CORE_ID( xLowestPriorityCore ) )
{ {
rtos_printf( "going to interrupt core %d which is running %s to place the task %s that was just replaced with %s on core %d\n",
xLowestPriorityCore,
pxCurrentTCBs[ xLowestPriorityCore ]->pcTaskName,
pxPreviousTCB->pcTaskName,
pxCurrentTCBs[ xCoreID ]->pcTaskName,
xCoreID );
prvYieldCore( xLowestPriorityCore ); prvYieldCore( xLowestPriorityCore );
} }
} }
@ -1600,12 +1591,10 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
{ {
if( pxCurrentTCBs[ xCoreID ] == NULL ) if( pxCurrentTCBs[ xCoreID ] == NULL )
{ {
rtos_printf( "adding idle task onto core %d\n", xCoreID );
pxNewTCB->xTaskRunState = xCoreID; pxNewTCB->xTaskRunState = xCoreID;
#if ( configUSE_CORE_EXCLUSION == 1 ) #if ( configUSE_CORE_EXCLUSION == 1 )
{ {
pxNewTCB->uxCoreExclude = ~( 1 << xCoreID ); pxNewTCB->uxCoreExclude = ~( 1 << xCoreID );
rtos_printf( "Set exclusion mask to %08x\n", pxNewTCB->uxCoreExclude );
} }
#endif #endif
pxCurrentTCBs[ xCoreID ] = pxNewTCB; pxCurrentTCBs[ xCoreID ] = pxNewTCB;
@ -1697,7 +1686,6 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
* no longer running. */ * no longer running. */
if( xTaskRunningOnCore != taskTASK_NOT_RUNNING ) if( xTaskRunningOnCore != taskTASK_NOT_RUNNING )
{ {
/*rtos_printf("Task %s is running on core %d and is now marked for deletion.\n", pxTCB->pcTaskName, xTaskRunningOnCore ); */
/* A running task is being deleted. This cannot complete within the /* A running task is being deleted. This cannot complete within the
* task itself, as a context switch to another task is required. * task itself, as a context switch to another task is required.
@ -1724,7 +1712,6 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
} }
else else
{ {
/*rtos_printf("Task %s is not running and will now be deleted.\n", pxTCB->pcTaskName ); */
--uxCurrentNumberOfTasks; --uxCurrentNumberOfTasks;
traceTASK_DELETE( pxTCB ); traceTASK_DELETE( pxTCB );
prvDeleteTCB( pxTCB ); prvDeleteTCB( pxTCB );
@ -1741,7 +1728,6 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
xCoreID = portGET_CORE_ID(); xCoreID = portGET_CORE_ID();
/*rtos_printf("Task deleted, yield core %d.\n", xTaskRunningOnCore ); */
if( xTaskRunningOnCore == xCoreID ) if( xTaskRunningOnCore == xCoreID )
{ {
@ -2240,7 +2226,6 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
if( ( uxCoreExclude & ( 1 << xCoreID ) ) != 0 ) if( ( uxCoreExclude & ( 1 << xCoreID ) ) != 0 )
{ {
rtos_printf( "New core exclusion mask on %s prevents it from running any longer on core %d\n", pxTCB->pcTaskName, xCoreID );
prvYieldCore( xCoreID ); prvYieldCore( xCoreID );
} }
} }
@ -2389,7 +2374,6 @@ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
{ {
if( xSchedulerRunning != pdFALSE ) if( xSchedulerRunning != pdFALSE )
{ {
/*rtos_printf("Yield Core %d for task %s\n", xTaskRunningOnCore, pxTCB->pcTaskName ); */
if( xTaskRunningOnCore == portGET_CORE_ID() ) if( xTaskRunningOnCore == portGET_CORE_ID() )
{ {
/* The current task has just been suspended. */ /* The current task has just been suspended. */
@ -2759,13 +2743,6 @@ void vTaskStartScheduler( void )
traceTASK_SWITCHED_IN(); traceTASK_SWITCHED_IN();
rtos_printf( "Scheduler starting, top priority is %d:\n", uxTopReadyPriority );
for( int i = 0; i < configNUM_CORES; i++ )
{
rtos_printf( "\tCore %d: Task %s running on core: %d\n", i, pxCurrentTCBs[ i ]->pcTaskName, pxCurrentTCBs[ i ]->xTaskRunState );
}
/* Setting up the timer tick is hardware specific and thus in the /* Setting up the timer tick is hardware specific and thus in the
* portable interface. */ * portable interface. */
if( xPortStartScheduler() != pdFALSE ) if( xPortStartScheduler() != pdFALSE )