mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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Updates to CM3_MPU GCC port
- System calls are now only allowed from kernel code. This change can be turned on or off using configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY. - MPU is disabled before reprogramming it and enabled afterwards to be compliant with ARM recommendations.
This commit is contained in:
Gaurav Aggarwal
parent
42a0eaafdc
commit
e058a65b16
@ -30,8 +30,8 @@
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*----------------------------------------------------------*/
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/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
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all the API functions to use the MPU wrappers. That should only be done when
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task.h is included from an application file. */
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* all the API functions to use the MPU wrappers. That should only be done when
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* task.h is included from an application file. */
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#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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/* Scheduler includes. */
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@ -46,7 +46,7 @@ task.h is included from an application file. */
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#define portNVIC_SYSTICK_CLK ( 1UL << 2UL )
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#else
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/* The way the SysTick is clocked is not modified in case it is not the same
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as the core. */
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* as the core. */
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#define portNVIC_SYSTICK_CLK ( 0 )
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#endif
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@ -86,21 +86,22 @@ task.h is included from an application file. */
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#define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
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/* Constants required to check the validity of an interrupt priority. */
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#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
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#define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
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#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
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#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
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#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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#define portPRIGROUP_SHIFT ( 8UL )
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#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
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#define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
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#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
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#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
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#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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#define portPRIGROUP_SHIFT ( 8UL )
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/* Offsets in the stack to the parameters when inside the SVC handler. */
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#define portOFFSET_TO_PC ( 6 )
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/* For strict compliance with the Cortex-M spec the task start address should
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have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
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#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
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* have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
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#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
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/*-----------------------------------------------------------*/
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/*
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* Configure a number of standard MPU regions that are used by all tasks.
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@ -171,8 +172,8 @@ extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
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/*-----------------------------------------------------------*/
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/* Each task maintains its own interrupt status in the critical nesting
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variable. Note this is not saved as part of the task context as context
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switches can only occur when uxCriticalNesting is zero. */
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* variable. Note this is not saved as part of the task context as context
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* switches can only occur when uxCriticalNesting is zero. */
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static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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/*
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@ -185,7 +186,6 @@ static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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static uint32_t ulMaxPRIGROUPValue = 0;
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static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
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#endif /* configASSERT_DEFINED */
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/*-----------------------------------------------------------*/
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/*
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@ -194,7 +194,7 @@ static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )
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{
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/* Simulate the stack frame as it would be created by a context switch
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interrupt. */
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* interrupt. */
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pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
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*pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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pxTopOfStack--;
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@ -240,10 +240,25 @@ void vPortSVCHandler( void )
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static void prvSVCHandler( uint32_t *pulParam )
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{
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uint8_t ucSVCNumber;
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uint32_t ulPC;
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#if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
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#if defined( __ARMCC_VERSION )
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/* Declaration when these variable are defined in code instead of being
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* exported from linker scripts. */
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extern uint32_t * __syscalls_flash_start__;
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extern uint32_t * __syscalls_flash_end__;
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#else
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/* Declaration when these variable are exported from linker scripts. */
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extern uint32_t __syscalls_flash_start__[];
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extern uint32_t __syscalls_flash_end__[];
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#endif /* #if defined( __ARMCC_VERSION ) */
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#endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
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/* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first
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* argument (r0) is pulParam[ 0 ]. */
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ulPC = pulParam[ portOFFSET_TO_PC ];
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ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
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/* The stack contains: r0, r1, r2, r3, r12, r14, the return address and
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xPSR. The first argument (r0) is pulParam[ 0 ]. */
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ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];
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switch( ucSVCNumber )
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{
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case portSVC_START_SCHEDULER : portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;
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@ -252,14 +267,32 @@ uint8_t ucSVCNumber;
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case portSVC_YIELD : portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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/* Barriers are normally not required
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but do ensure the code is completely
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within the specified behaviour for the
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architecture. */
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* but do ensure the code is completely
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* within the specified behaviour for the
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* architecture. */
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__asm volatile( "dsb" ::: "memory" );
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__asm volatile( "isb" );
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break;
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#if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
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case portSVC_RAISE_PRIVILEGE : /* Only raise the privilege, if the
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* svc was raised from any of the
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* system calls. */
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if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
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ulPC <= ( uint32_t ) __syscalls_flash_end__ )
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{
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__asm volatile
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(
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" mrs r1, control \n" /* Obtain current control value. */
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" bic r1, #1 \n" /* Set privilege bit. */
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" msr control, r1 \n" /* Write back new control value. */
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::: "r1", "memory"
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);
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}
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break;
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#else
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case portSVC_RAISE_PRIVILEGE : __asm volatile
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(
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" mrs r1, control \n" /* Obtain current control value. */
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@ -268,6 +301,7 @@ uint8_t ucSVCNumber;
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::: "r1", "memory"
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);
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break;
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#endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
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default : /* Unknown SVC call. */
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break;
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@ -287,9 +321,23 @@ static void prvRestoreContextOfFirstTask( void )
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" ldr r1, [r3] \n"
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" ldr r0, [r1] \n" /* The first item in the TCB is the task top of stack. */
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" add r1, r1, #4 \n" /* Move onto the second item in the TCB... */
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" \n"
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" dmb \n" /* Complete outstanding transfers before disabling MPU. */
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" ldr r2, =0xe000ed94 \n" /* MPU_CTRL register. */
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" ldr r3, [r2] \n" /* Read the value of MPU_CTRL. */
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" bic r3, #1 \n" /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
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" str r3, [r2] \n" /* Disable MPU. */
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" \n"
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" ldr r2, =0xe000ed9c \n" /* Region Base Address register. */
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" ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers. */
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" stmia r2!, {r4-r11} \n" /* Write 4 sets of MPU registers. */
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" \n"
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" ldr r2, =0xe000ed94 \n" /* MPU_CTRL register. */
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" ldr r3, [r2] \n" /* Read the value of MPU_CTRL. */
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" orr r3, #1 \n" /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
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" str r3, [r2] \n" /* Enable MPU. */
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" dsb \n" /* Force memory writes before continuing. */
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" \n"
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" ldmia r0!, {r3, r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry. */
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" msr control, r3 \n"
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" msr psp, r0 \n" /* Restore the task stack pointer. */
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@ -310,7 +358,7 @@ static void prvRestoreContextOfFirstTask( void )
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BaseType_t xPortStartScheduler( void )
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{
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/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See
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http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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* http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
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#if( configASSERT_DEFINED == 1 )
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@ -320,15 +368,15 @@ BaseType_t xPortStartScheduler( void )
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volatile uint8_t ucMaxPriorityValue;
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/* Determine the maximum priority from which ISR safe FreeRTOS API
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functions can be called. ISR safe functions are those that end in
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"FromISR". FreeRTOS maintains separate thread and ISR API functions to
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ensure interrupt entry is as fast and simple as possible.
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* functions can be called. ISR safe functions are those that end in
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* "FromISR". FreeRTOS maintains separate thread and ISR API functions
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* to ensure interrupt entry is as fast and simple as possible.
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Save the interrupt priority value that is about to be clobbered. */
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* Save the interrupt priority value that is about to be clobbered. */
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ulOriginalPriority = *pucFirstUserPriorityRegister;
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/* Determine the number of priority bits available. First write to all
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possible bits. */
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* possible bits. */
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*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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/* Read the value back to see how many bits stuck. */
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@ -338,7 +386,7 @@ BaseType_t xPortStartScheduler( void )
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ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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/* Calculate the maximum acceptable priority group value for the number
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of bits read back. */
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* of bits read back. */
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ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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{
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@ -349,8 +397,8 @@ BaseType_t xPortStartScheduler( void )
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#ifdef __NVIC_PRIO_BITS
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{
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/* Check the CMSIS configuration that defines the number of
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priority bits matches the number of priority bits actually queried
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from the hardware. */
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* priority bits matches the number of priority bits actually queried
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* from the hardware. */
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configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
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}
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#endif
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@ -358,26 +406,26 @@ BaseType_t xPortStartScheduler( void )
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#ifdef configPRIO_BITS
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{
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/* Check the FreeRTOS configuration that defines the number of
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priority bits matches the number of priority bits actually queried
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from the hardware. */
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* priority bits matches the number of priority bits actually queried
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* from the hardware. */
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configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
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}
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#endif
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/* Shift the priority group value back to its position within the AIRCR
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register. */
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* register. */
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ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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/* Restore the clobbered interrupt priority register to its original
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value. */
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* value. */
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*pucFirstUserPriorityRegister = ulOriginalPriority;
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}
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#endif /* conifgASSERT_DEFINED */
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/* Make PendSV and SysTick the same priority as the kernel, and the SVC
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handler higher priority so it can be used to exit a critical section (where
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lower priorities are masked). */
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* handler higher priority so it can be used to exit a critical section (where
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* lower priorities are masked). */
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portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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@ -385,7 +433,7 @@ BaseType_t xPortStartScheduler( void )
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prvSetupMPU();
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/* Start the timer that generates the tick ISR. Interrupts are disabled
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here already. */
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* here already. */
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vPortSetupTimerInterrupt();
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/* Initialise the critical nesting count ready for the first task. */
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@ -413,7 +461,7 @@ BaseType_t xPortStartScheduler( void )
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void vPortEndScheduler( void )
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{
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/* Not implemented in ports where there is nothing to return to.
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Artificially force an assert. */
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* Artificially force an assert. */
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configASSERT( uxCriticalNesting == 1000UL );
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}
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/*-----------------------------------------------------------*/
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@ -471,9 +519,23 @@ void xPortPendSVHandler( void )
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" ldr r1, [r3] \n"
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" ldr r0, [r1] \n" /* The first item in the TCB is the task top of stack. */
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" add r1, r1, #4 \n" /* Move onto the second item in the TCB... */
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" \n"
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" dmb \n" /* Complete outstanding transfers before disabling MPU. */
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" ldr r2, =0xe000ed94 \n" /* MPU_CTRL register. */
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" ldr r3, [r2] \n" /* Read the value of MPU_CTRL. */
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" bic r3, #1 \n" /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
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" str r3, [r2] \n" /* Disable MPU. */
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" \n"
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" ldr r2, =0xe000ed9c \n" /* Region Base Address register. */
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" ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers. */
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" stmia r2!, {r4-r11} \n" /* Write 4 sets of MPU registers. */
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" \n"
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" ldr r2, =0xe000ed94 \n" /* MPU_CTRL register. */
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" ldr r3, [r2] \n" /* Read the value of MPU_CTRL. */
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" orr r3, #1 \n" /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
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" str r3, [r2] \n" /* Enable MPU. */
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" dsb \n" /* Force memory writes before continuing. */
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" \n"
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" ldmia r0!, {r3, r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry. */
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" msr control, r3 \n"
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" \n"
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@ -542,8 +604,8 @@ extern uint32_t __privileged_data_end__[];
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( portMPU_REGION_ENABLE );
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/* Setup the first 16K for privileged only access (even though less
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than 10K is actually being used). This is where the kernel code is
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placed. */
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* than 10K is actually being used). This is where the kernel code is
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* placed. */
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portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
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( portMPU_REGION_VALID ) |
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( portPRIVILEGED_FLASH_REGION );
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@ -554,7 +616,7 @@ extern uint32_t __privileged_data_end__[];
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( portMPU_REGION_ENABLE );
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/* Setup the privileged data RAM region. This is where the kernel data
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is placed. */
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* is placed. */
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portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
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( portMPU_REGION_VALID ) |
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( portPRIVILEGED_RAM_REGION );
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@ -565,7 +627,7 @@ extern uint32_t __privileged_data_end__[];
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( portMPU_REGION_ENABLE );
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/* By default allow everything to access the general peripherals. The
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system peripherals and registers are protected. */
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* system peripherals and registers are protected. */
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portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |
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( portMPU_REGION_VALID ) |
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( portGENERAL_PERIPHERALS_REGION );
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@ -588,7 +650,7 @@ static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
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uint32_t ulRegionSize, ulReturnValue = 4;
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/* 32 is the smallest region size, 31 is the largest valid value for
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ulReturnValue. */
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* ulReturnValue. */
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for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
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{
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if( ulActualSizeInBytes <= ulRegionSize )
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@ -602,7 +664,7 @@ uint32_t ulRegionSize, ulReturnValue = 4;
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}
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/* Shift the code by one before returning so it can be written directly
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into the the correct bit position of the attribute register. */
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* into the the correct bit position of the attribute register. */
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return ( ulReturnValue << 1UL );
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}
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/*-----------------------------------------------------------*/
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@ -661,7 +723,7 @@ uint32_t ul;
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( portMPU_REGION_ENABLE );
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/* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
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just removed the privileged only parameters. */
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* just removed the privileged only parameters. */
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xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
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( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
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( portMPU_REGION_VALID ) |
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@ -683,9 +745,9 @@ uint32_t ul;
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else
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{
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/* This function is called automatically when the task is created - in
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which case the stack region parameters will be valid. At all other
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times the stack parameters will not be valid and it is assumed that the
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stack region has already been configured. */
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* which case the stack region parameters will be valid. At all other
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* times the stack parameters will not be valid and it is assumed that the
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* stack region has already been configured. */
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if( ulStackDepth > 0 )
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{
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/* Define the region that allows access to the stack. */
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@ -708,8 +770,8 @@ uint32_t ul;
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if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
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{
|
||||
/* Translate the generic region definition contained in
|
||||
xRegions into the CM3 specific MPU settings that are then
|
||||
stored in xMPUSettings. */
|
||||
* xRegions into the CM3 specific MPU settings that are then
|
||||
* stored in xMPUSettings. */
|
||||
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
|
||||
( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
|
||||
( portMPU_REGION_VALID ) |
|
||||
@ -750,48 +812,46 @@ uint32_t ul;
|
||||
ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
|
||||
|
||||
/* The following assertion will fail if a service routine (ISR) for
|
||||
an interrupt that has been assigned a priority above
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
|
||||
function. ISR safe FreeRTOS API functions must *only* be called
|
||||
from interrupts that have been assigned a priority at or below
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY.
|
||||
* an interrupt that has been assigned a priority above
|
||||
* configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
|
||||
* function. ISR safe FreeRTOS API functions must *only* be called
|
||||
* from interrupts that have been assigned a priority at or below
|
||||
* configMAX_SYSCALL_INTERRUPT_PRIORITY.
|
||||
|
||||
Numerically low interrupt priority numbers represent logically high
|
||||
interrupt priorities, therefore the priority of the interrupt must
|
||||
be set to a value equal to or numerically *higher* than
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY.
|
||||
* Numerically low interrupt priority numbers represent logically high
|
||||
* interrupt priorities, therefore the priority of the interrupt must
|
||||
* be set to a value equal to or numerically *higher* than
|
||||
* configMAX_SYSCALL_INTERRUPT_PRIORITY.
|
||||
|
||||
Interrupts that use the FreeRTOS API must not be left at their
|
||||
default priority of zero as that is the highest possible priority,
|
||||
which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
|
||||
and therefore also guaranteed to be invalid.
|
||||
* Interrupts that use the FreeRTOS API must not be left at their
|
||||
* default priority of zero as that is the highest possible priority,
|
||||
* which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
|
||||
* and therefore also guaranteed to be invalid.
|
||||
|
||||
FreeRTOS maintains separate thread and ISR API functions to ensure
|
||||
interrupt entry is as fast and simple as possible.
|
||||
* FreeRTOS maintains separate thread and ISR API functions to ensure
|
||||
* interrupt entry is as fast and simple as possible.
|
||||
|
||||
The following links provide detailed information:
|
||||
http://www.freertos.org/RTOS-Cortex-M3-M4.html
|
||||
http://www.freertos.org/FAQHelp.html */
|
||||
* The following links provide detailed information:
|
||||
* http://www.freertos.org/RTOS-Cortex-M3-M4.html
|
||||
* http://www.freertos.org/FAQHelp.html */
|
||||
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
|
||||
}
|
||||
|
||||
/* Priority grouping: The interrupt controller (NVIC) allows the bits
|
||||
that define each interrupt's priority to be split between bits that
|
||||
define the interrupt's pre-emption priority bits and bits that define
|
||||
the interrupt's sub-priority. For simplicity all bits must be defined
|
||||
to be pre-emption priority bits. The following assertion will fail if
|
||||
this is not the case (if some bits represent a sub-priority).
|
||||
* that define each interrupt's priority to be split between bits that
|
||||
* define the interrupt's pre-emption priority bits and bits that define
|
||||
* the interrupt's sub-priority. For simplicity all bits must be defined
|
||||
* to be pre-emption priority bits. The following assertion will fail if
|
||||
* this is not the case (if some bits represent a sub-priority).
|
||||
|
||||
If the application only uses CMSIS libraries for interrupt
|
||||
configuration then the correct setting can be achieved on all Cortex-M
|
||||
devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
|
||||
scheduler. Note however that some vendor specific peripheral libraries
|
||||
assume a non-zero priority group setting, in which cases using a value
|
||||
of zero will result in unpredicable behaviour. */
|
||||
* If the application only uses CMSIS libraries for interrupt
|
||||
* configuration then the correct setting can be achieved on all Cortex-M
|
||||
* devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
|
||||
* scheduler. Note however that some vendor specific peripheral libraries
|
||||
* assume a non-zero priority group setting, in which cases using a value
|
||||
* of zero will result in unpredicable behaviour. */
|
||||
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
|
||||
}
|
||||
|
||||
#endif /* configASSERT_DEFINED */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
||||
|
||||
@ -73,12 +73,13 @@ typedef unsigned long UBaseType_t;
|
||||
#define portUSING_MPU_WRAPPERS 1
|
||||
#define portPRIVILEGE_BIT ( 0x80000000UL )
|
||||
|
||||
#define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL )
|
||||
#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL )
|
||||
#define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL )
|
||||
#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL )
|
||||
#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
|
||||
#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
|
||||
#define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL )
|
||||
#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL )
|
||||
#define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL )
|
||||
#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL )
|
||||
#define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL )
|
||||
#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
|
||||
#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
|
||||
|
||||
#define portUNPRIVILEGED_FLASH_REGION ( 0UL )
|
||||
#define portPRIVILEGED_FLASH_REGION ( 1UL )
|
||||
@ -293,6 +294,11 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
|
||||
|
||||
#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
|
||||
|
||||
#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
|
||||
#warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security."
|
||||
#define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0
|
||||
#endif
|
||||
/*-----------------------------------------------------------*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user