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Remove Unused Code and Preprocessor Directives in RP2040 Port (#1324)

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* Remove redundant code and preprocessor directives

* Remove more redundant code and directives
This commit is contained in:
Pascal Reich 2025-10-08 08:36:45 -04:00 committed by GitHub
parent a1f6e1f64f
commit e5987bbdb2
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1 changed files with 21 additions and 39 deletions
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60
portable/ThirdParty/GCC/RP2040/port.c vendored
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@ -243,35 +243,28 @@ void vPortStartFirstTask( void )
" ldr r0, [r0] \n" " ldr r0, [r0] \n"
" msr msp, r0 \n" /* Set the msp back to the start of the stack. */ " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
#endif /* configRESET_STACK_POINTER */ #endif /* configRESET_STACK_POINTER */
#if ( configNUMBER_OF_CORES != 1 )
" adr r1, ulAsmLocals \n" /* Get the location of the current TCB for the current core. */ " adr r1, ulAsmLocals \n" /* Get the location of the current TCB for the current core. */
" ldmia r1!, {r2, r3} \n" " ldmia r1!, {r2, r3} \n"
" ldr r2, [r2] \n" /* r2 = Core number */ " ldr r2, [r2] \n" /* r2 = Core number */
" lsls r2, #2 \n" " lsls r2, #2 \n"
" ldr r3, [r3, r2] \n" /* r3 = pxCurrentTCBs[get_core_num()] */ " ldr r3, [r3, r2] \n" /* r3 = pxCurrentTCBs[get_core_num()] */
#else /* configNUMBER_OF_CORES != 1 */ " ldr r0, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */
" ldr r3, =pxCurrentTCBs \n" " adds r0, #32 \n" /* Discard everything up to r0. */
" ldr r3, [r3] \n" /* r3 = pxCurrentTCBs[0] */ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
#endif /* configNUMBER_OF_CORES != 1 */ " movs r0, #2 \n" /* Switch to the psp stack. */
" ldr r0, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */ " msr CONTROL, r0 \n"
" adds r0, #32 \n" /* Discard everything up to r0. */ " isb \n"
" msr psp, r0 \n" /* This is now the new top of stack to use in the task. */ " pop {r0-r5} \n" /* Pop the registers that are saved automatically. */
" movs r0, #2 \n" /* Switch to the psp stack. */ " mov lr, r5 \n" /* lr is now in r5. */
" msr CONTROL, r0 \n" " pop {r3} \n" /* Return address is now in r3. */
" isb \n" " pop {r2} \n" /* Pop and discard XPSR. */
" pop {r0-r5} \n" /* Pop the registers that are saved automatically. */ " cpsie i \n" /* The first task has its context and interrupts can be enabled. */
" mov lr, r5 \n" /* lr is now in r5. */ " bx r3 \n" /* Finally, jump to the user defined task code. */
" pop {r3} \n" /* Return address is now in r3. */
" pop {r2} \n" /* Pop and discard XPSR. */
" cpsie i \n" /* The first task has its context and interrupts can be enabled. */
" bx r3 \n" /* Finally, jump to the user defined task code. */
#if configNUMBER_OF_CORES != 1
" \n" " \n"
" .align 4 \n" " .align 4 \n"
"ulAsmLocals: \n" "ulAsmLocals: \n"
" .word 0xD0000000 \n" /* SIO */ " .word 0xD0000000 \n" /* SIO */
" .word pxCurrentTCBs \n" " .word pxCurrentTCBs \n"
#endif /* portRUNNING_ON_BOTH_CORES */
); );
#endif /* if ( configNUMBER_OF_CORES == 1 ) */ #endif /* if ( configNUMBER_OF_CORES == 1 ) */
} }
@ -369,14 +362,11 @@ void vPortStartFirstTask( void )
spin_lock_claim( configSMP_SPINLOCK_0 ); spin_lock_claim( configSMP_SPINLOCK_0 );
spin_lock_claim( configSMP_SPINLOCK_1 ); spin_lock_claim( configSMP_SPINLOCK_1 );
#if configNUMBER_OF_CORES != 1 ucPrimaryCoreNum = configTICK_CORE;
ucPrimaryCoreNum = configTICK_CORE; configASSERT( get_core_num() == 0 ); /* we must be started on core 0 */
configASSERT( get_core_num() == 0 ); /* we must be started on core 0 */ multicore_reset_core1();
multicore_reset_core1(); multicore_launch_core1( prvDisableInterruptsAndPortStartSchedulerOnCore );
multicore_launch_core1( prvDisableInterruptsAndPortStartSchedulerOnCore );
#else
ucPrimaryCoreNum = get_core_num();
#endif
xPortStartSchedulerOnCore(); xPortStartSchedulerOnCore();
/* Should not get here! */ /* Should not get here! */
@ -618,13 +608,9 @@ void xPortPendSVHandler( void )
" \n" " \n"
" adr r0, ulAsmLocals2 \n" /* Get the location of the current TCB for the current core. */ " adr r0, ulAsmLocals2 \n" /* Get the location of the current TCB for the current core. */
" ldmia r0!, {r2, r3} \n" " ldmia r0!, {r2, r3} \n"
#if configNUMBER_OF_CORES != 1 " ldr r0, [r2] \n" /* r0 = Core number */
" ldr r0, [r2] \n" /* r0 = Core number */ " lsls r0, r0, #2 \n"
" lsls r0, r0, #2 \n" " adds r3, r0 \n" /* r3 = &pxCurrentTCBs[get_core_num()] */
" adds r3, r0 \n" /* r3 = &pxCurrentTCBs[get_core_num()] */
#else
" \n" /* r3 = &pxCurrentTCBs[0] */
#endif /* portRUNNING_ON_BOTH_CORES */
" ldr r0, [r3] \n" /* r0 = pxCurrentTCB */ " ldr r0, [r3] \n" /* r0 = pxCurrentTCB */
" \n" " \n"
" subs r1, r1, #32 \n" /* Make space for the remaining low registers. */ " subs r1, r1, #32 \n" /* Make space for the remaining low registers. */
@ -658,11 +644,7 @@ void xPortPendSVHandler( void )
" subs r1, r1, #48 \n" " subs r1, r1, #48 \n"
" stmia r1!, {r4-r7} \n" " stmia r1!, {r4-r7} \n"
#endif /* portUSE_DIVIDER_SAVE_RESTORE */ #endif /* portUSE_DIVIDER_SAVE_RESTORE */
#if configNUMBER_OF_CORES != 1 " ldr r0, [r2] \n" /* r0 = Core number */
" ldr r0, [r2] \n" /* r0 = Core number */
#else
" movs r0, #0 \n"
#endif /* configNUMBER_OF_CORES != 1 */
" push {r3, r14} \n" " push {r3, r14} \n"
" cpsid i \n" " cpsid i \n"
" bl vTaskSwitchContext \n" " bl vTaskSwitchContext \n"