Fix several documentation and example-code issues in the kernel header comments:
* queue.h: remove a stray semicolon after the 'if' and correct the
xHigherPriorityTaskWoken variable casing in the xQueueReceiveFromISR()
example; add the missing comma between parameters in the
xQueueGenericSend() prototype example.
* list.h: correct the doxygen \page tag for listGET_ITEM_VALUE_OF_HEAD_ENTRY.
* task.h: fix the uxIndexToCLear typo (-> uxIndexToClear).
These are documentation/example only changes that do not affect the
compiled library.
Signed-off-by: chenrongjun <chenrongjun@zepp.com>
The comment after vPortSetupTimerInterrupt in GCC and IAR RISC-V port.c duplicated configMTIME_BASE_ADDRESS and omitted configMTIMECMP_BASE_ADDRESS. Align the comment with the matching #if condition.
According to the RISC-V Privileged Architecture Specification (20211203),
writing Initial or Clean to the FS field of mstatus may result in the FS
value getting set to Dirty in some implementations. This means we cannot
rely on reading back the same FS value after writing to mstatus.
Previously, the context restore code would:
1. Write an FS value to mstatus
2. Read mstatus again at a later point
3. Use the read FS value to determine FPU status
This change updates the context restore code to use the mstatus value
from the saved context instead of re-reading mstatus after writing to
it. This required chaning the location of the mstatus slot in the
context.
Fixes: https://github.com/FreeRTOS/FreeRTOS-Kernel/issues/1327
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Use architecture-dependent UBaseType_t instead of fixed type for
ullMachineTimerCompareRegisterBase. This type is defined to uint32_t or
uint64_t based on XLEN, resolving warnings on 32-bit platforms.
Reported by landretk@ on the PR FreeRTOS/FreeRTOS-Kernel#1176.
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
RISC-V: refine fpu reg context offset
pxCode and mstatus stored at index 0 and 1 are based on XLEN.
Therefore, the correct formula to calculate the FPU register index
should be ( ( 2 * portWORD_SIZE ) + ( regIndex * portFPU_REG_SIZE ) ).
Signed-off-by: wangfei_chen <wangfei_chen@realsil.com.cn>
* port: riscv: Split the number of registers and the size of the context
* port: riscv: Create some macros for the FPU context
* port: riscv: Add a couple of macros that store fpu context
* port: riscv: Update the stack init function to include the fpu context size
* port: riscv: Add a chip_specific_extensions file that includes the F extension
* Update dictionary to include some risc-v instructions
* port: riscv: Fix a few typos
* port: riscv: Apply @aggarg's sugestions
Related to #189
Update `configMTIMECMP_BASE_ADDRESS` to be stored in a 64-bit integer.
* Change the type of `ullMachineTimerCompareRegisterBase` to `uint64_t` in `portable/GCC/RISC-V/port.c`.
* Change the type of `ullMachineTimerCompareRegisterBase` to `uint64_t` in `portable/IAR/RISC-V/port.c`.
* Update the initialization of `ullMachineTimerCompareRegisterBase` to use `configMTIMECMP_BASE_ADDRESS` in both files.
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
* Introduce portHAS_NESTED_INTERRUPTS to identify if port has nested interrupt or not.
* Update atomic.h to use portHAS_NESTED_INTERRUPTS instead of portSET_INTERRUPT_MASK_FROM_ISR definition.
---------
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: ActoryOu <jay2002824@gmail.com>
* Support configurable RISC-V chip extension
Added the FREERTOS_RISCV_EXTENSION option to allow the user
to select which chip extension they want included. Removed the
port for pulpino to instead use the new option.
* Add port GCC_RISC_V_GENERIC and IAR_RISC_V_GENERIC
* Add two rics-v generic ports to support FREERTOS_RISCV_EXTENSION
config
---------
Co-authored-by: Joe Benczarski <jbenczarski@trijicon.com>
Co-authored-by: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com>
Co-authored-by: Ching-Hsin Lee <chinglee@amazon.com>
Co-authored-by: kar-rahul-aws <118818625+kar-rahul-aws@users.noreply.github.com>
Co-authored-by: Soren Ptak <ptaksoren@gmail.com>
Add trace hook macro for most ports
In pull request #659 we introduced better support for tracing
tools like systemview. This patchset adds support for more
ports as requested in the original pull request.
* Use new version of CI-CD Actions
* Use cSpell spell check, and use ubuntu-20.04 for formatting check
* Format and spell check all files in the portable directory
* Remove the https:// from #errors and #warnings as uncrustify attempts to change it to /*
* Use checkout@v3 instead of checkout@v2 on all jobs
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Adds RV32E support to the IAR port. This is done by
reducing our register usage to the first 16 registers
only.
Influenced by changes in https://github.com/FreeRTOS/FreeRTOS-Kernel/pull/543
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
* Change vPortSetupTimerInterrupt in order to have 64bits access on rv64
* Support RV32E - RISC-V architecture (GCC)
Signed-off-by: Emmanuel Puerto <emmanuel.puerto@sifive.com>
* Support FPU - RISC-V architecture (GCC)
Signed-off-by: Emmanuel Puerto <emmanuel.puerto@sifive.com>
* Fix interrupt managment and FPU initialization
* Style: make freertos.org = FreeRTOS.org also add https
* Style: Fix freertos into FreeRTOS
* Style: Fix freertos into FreeRTOS
Co-authored-by: Alfred Gedeon <gedeonag@amazon.com>
* Style: Change FreeRTOS websites in comments
* Style: Change freertos to FreeRTOS in comments
* Style: Remove broken link
Co-authored-by: Alfred Gedeon <gedeonag@amazon.com>
