7 Commits

Author	SHA1	Message	Date
Yuhui.Zheng	589dd9f149	Update version number in readiness for V10.3.0 release. Sync SVN with reviewed release candidate.	2020-02-07 20:14:50 +00:00
Richard Barry	7bea399061	Update libraries and sundry check-ins ready for the V10.3.0 kernel release.	2020-02-06 18:52:35 +00:00
Richard Barry	fbb23055cd	Replace portasmHAS_CLINT with configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions in the GCC RISC-V port - portasmHAS_CLIT will still work by deriving the new definitions from the old.	2020-01-07 01:14:36 +00:00
Richard Barry	b51529a284	Update version number ready for next release.	2019-05-11 01:47:37 +00:00
Richard Barry	2265d70499	Correcting spelling mistakes in comments only.	2019-03-08 17:30:49 +00:00
Richard Barry	58ba10eee8	Update version number in readiness for V10.2.0 release.	2019-02-17 22:36:16 +00:00
Richard Barry	b2b1b09ea5	Fix bug in core_cm3.c atomic macros. ... Rename the portable/GCC/RISC-V-RV32 directory to just RISC-V as also adding support for 64-bit cores.	2019-02-16 01:08:38 +00:00