3 Commits

Author	SHA1	Message	Date
Richard Barry	80c1cb5de1	Correct code comments that referred to taskYIELD_FROM_ISR to portYIELD_FROM_ISR. ... Update RV32 port to use 16 byte-alignment all the time (only strictly necessary when using FLOP instructions).	2019-09-24 16:06:21 +00:00
Richard Barry	da3d370ff7	RISC-V port updates: The machine timer compare register can now be for any HART, and correct the sequence used to update the 64-bit machine timer compare register on 32-bit cores.	2019-09-04 15:46:45 +00:00
Richard Barry	ab41d89285	Add IAR RISC-V port to SVN - a work in progress.	2019-09-03 01:39:29 +00:00