Yuhui.Zheng
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0fe36e497d
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Nordic port. Notes for Richard -- the work items we discussed about for nrf52840-dk and Wiced_CY still remain. The only reason for this commit is we want to test out submodule.
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2019-09-24 22:26:36 +00:00 |
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Yuhui.Zheng
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35bc9d7938
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Revert 2728. Not because the files are still needed, but because we want to test out submodule.
Before further updating project files in GitHub, keeping an additional copy.
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2019-09-24 22:19:54 +00:00 |
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Yuhui.Zheng
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f001126ea8
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Wiced_CY port is not needed anymore. Use GCC/ARM_CRx_No_GIC instead.
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2019-09-24 20:56:55 +00:00 |
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Yuhui.Zheng
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6f958bbf80
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sync from github to svn: Xtensa GCC as-is.
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2019-09-20 22:09:21 +00:00 |
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Yuhui.Zheng
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1c5fcc7f05
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sync from github to svn: Wiced_CY for AFR Cypress ports.
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2019-09-20 20:52:30 +00:00 |
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Gaurav Aggarwal
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817783d75c
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Copyright updates from Cadence.
e1df894752
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2019-01-16 19:01:25 +00:00 |
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Richard Barry
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c6de0001fa
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Added uxTaskGetStackHighWaterMark2(), which is the same as uxTaskGetStackHighWaterMark() other than the return type.
Allows the task name parameter passed into xTaskCreate() to be NULL.
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2018-09-30 21:50:05 +00:00 |
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Gaurav Aggarwal
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56dc0dd9b4
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Merge bug fixes from Cadence
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2018-08-07 07:21:07 +00:00 |
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Richard Barry
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483f4a8c4b
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Small change to the directory name in which the RISC-V port is stored.
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2018-06-20 21:15:04 +00:00 |
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Richard Barry
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3d8d2f3cc8
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Add RISCV port layer.
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2018-06-20 19:21:18 +00:00 |
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Gaurav Aggarwal
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c4b1afc4ef
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Add Xtensa port
The project file is for Xtensa Xplorer simulator.
Also add tests for one size stream buffer.
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2018-06-14 19:43:17 +00:00 |
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