5 Commits

Author	SHA1	Message	Date
Richard Barry	f6edf4adf9	Update the RegTest.S file used by several GCC RISC-V demos to ensure correct alignment of constant loads from assembly code.	2019-10-14 00:16:25 +00:00
Richard Barry	96e61a10a5	Tidy up the RISC-V_RV32_SiFive_HiFive1_GCC demo ready for its eventual release.	2019-10-14 00:04:53 +00:00
Richard Barry	d4216903d9	Added the "full" demo to the RISC-V_RV32_SiFive_HiFive1_GCC demo - backup check in only as still a work in progress.	2019-10-13 22:53:00 +00:00
Richard Barry	71d9450836	RIS-V_RV32_SiFive_HiFive1_GCC project now running the blinky demo - still a work in progress.	2019-10-11 02:59:13 +00:00
Richard Barry	dbbebbfcbc	RISC-V-RV32_SiFive_HiFive1_GCC project is now also building the FreeRTOS kernel code - but not using it yet - still a work in progress.	2019-10-10 17:54:56 +00:00