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Mono Color

• fb3eaeac40 Added additional xMessageBufferSpacesAvailable() (plural) to existing xMessageBufferSpaceAvailable() (singular) macro as the documentation muddled both. Added #define portPOINTER_SIZE_TYPE uint64_t to the 64-bit RISC-V port layer. Richard Barry 2019-05-13 03:14:05 +00:00
• b51529a284 Update version number ready for next release. Richard Barry 2019-05-11 01:47:37 +00:00
• 9e10b08a3a Delete the Release configuration from the NXP project. Gaurav Aggarwal 2019-05-11 00:53:34 +00:00
• db5d265c07 Removing obsolete code and files only. Richard Barry 2019-05-10 22:19:18 +00:00
• 53cb12e389 Add M7/M4 AMP demo. Richard Barry 2019-05-10 18:25:10 +00:00
• 0b1a025789 Add NXP libs needed to build the project Gaurav Aggarwal 2019-05-09 22:27:44 +00:00
• aa9c8d2697 Delete the not needed file missed in last commit Gaurav Aggarwal 2019-05-09 22:09:12 +00:00
• b9e379951a Do not strip required symbols when LTO is on Gaurav Aggarwal 2019-05-09 22:04:29 +00:00
• b6e5f96f0e Ensure that fault handlers are declared naked. Gaurav Aggarwal 2019-05-05 02:26:42 +00:00
• 2279a86566 Add ARMv8M demo project for NXP LPC55S69. Gaurav Aggarwal 2019-05-05 02:15:55 +00:00
• ae448fc952 Add Cortex M23 GCC and IAR ports. Add demo projects for Nuvoton NuMaker-PFM-2351. Gaurav Aggarwal 2019-05-02 21:08:28 +00:00
• 079d081346 Basic 64-bit RISC-V port now functional. RISC-V port layer automatically switches between 32-bit and 64-bit. Richard Barry 2019-04-29 00:57:14 +00:00
• 27ca5c8341 Added portMEMORY_BARRIER() implemented as __asm volatile( "" ::: "memory" ) into ARM Cortex-M33 ports to assist with link time optimisation. Richard Barry 2019-04-25 19:49:50 +00:00
• 84377442fc Added portMEMORY_BARRIER() implemented as __asm volatile( "" ::: "memory" ) into ARM GCC ports to assist with link time optimisation. Richard Barry 2019-04-21 20:15:34 +00:00
• 606845492b Fix potential memory leak in the Win32 FreeRTOS+TCP network interface initialisation sequence. Introduce portMEMORY_BARRIER() macro to assist with memory access ordering when suspending the scheduler if link time optimization is used. Richard Barry 2019-04-17 17:16:04 +00:00
• dd9a9710c6 Export port architecture name for COrtex-M33. This can be used by debuggers to find the port in-use to be able to correctly decode the context stored on the stack. Gaurav Aggarwal 2019-03-28 00:00:46 +00:00
• ba39a958b5 Fix spelling of priority in comments. Gaurav Aggarwal 2019-03-18 23:28:03 +00:00
• 12fb75be37 Fix warning portHAS_STACK_OVERFLOW_CHECKING not defined Gaurav Aggarwal 2019-03-13 21:10:44 +00:00
• 2265d70499 Correcting spelling mistakes in comments only. Richard Barry 2019-03-08 17:30:49 +00:00
• 06596c3192 Prepare the RISC-V port layer for addition of 64-bit port. Richard Barry 2019-03-08 17:03:43 +00:00
• 233285746e V10.2.0 Gaurav Aggarwal 2019-03-07 22:57:18 +00:00
• 50e67a89f1 Update version number in +TCP code. Richard Barry 2019-02-21 18:08:36 +00:00
• 5fe8465a35 Change type of usStackDepth to configSTACK_DEPTH_TYPE. Gaurav Aggarwal 2019-02-21 03:25:30 +00:00
• 5623c69748 Fix Build and Links failure in MPU projects. Minor cosmetic changes in some V8M files. Gaurav Aggarwal 2019-02-20 20:27:07 +00:00
• 8b6ab5f197 Add instructions on building the Cortex-M33 secure and non secure projects into the comments of that project and into a readme.txt file. Enable configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES setting to be used in statically allocated systems. Richard Barry 2019-02-20 17:55:59 +00:00
• ceeff14524 Set default value of configRUN_FREERTOS_SECURE_ONLY to 0. Gaurav Aggarwal 2019-02-20 00:40:46 +00:00
• 5849459c65 Add support for running FreeRTOS on Secure Side only in Cortex M33 port. Also, change spaces to tabs. Gaurav Aggarwal 2019-02-20 00:25:45 +00:00
• c3c9c12ce2 Update the common demo death.c to use the updated macro name to give it a secure context. Richard Barry 2019-02-19 02:57:44 +00:00
• ce576f3683 First Official Release of ARMV8M Support. This release removes Pre-Release from all the ARMv8M files licensees. Gaurav Aggarwal 2019-02-19 02:30:32 +00:00
• 58ba10eee8 Update version number in readiness for V10.2.0 release. Richard Barry 2019-02-17 22:36:16 +00:00
• 55ad3861c5 Sync the Renesas port to AFR Git Repo Gaurav Aggarwal 2019-02-17 01:27:16 +00:00
• 0de2a2758a Fix definition of tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE Gaurav Aggarwal 2019-02-17 01:24:58 +00:00
• 2c88fb7fa1 Fix build failure when dynamic allocation is not enabled. Gaurav Aggarwal 2019-02-16 20:21:47 +00:00
• 6844bef74f Replace the pdf RISC-V documentation with links to the documentation web pages. Richard Barry 2019-02-16 01:15:33 +00:00
• b2b1b09ea5 Fix bug in core_cm3.c atomic macros. Rename the portable/GCC/RISC-V-RV32 directory to just RISC-V as also adding support for 64-bit cores. Richard Barry 2019-02-16 01:08:38 +00:00
• 3153131fa7 Add Dornerworks attribution to makefiles that build the Freedom Studio RISC-V project. Richard Barry 2019-02-12 02:43:28 +00:00
• 7e08fd6d07 Add makefiles that build the FreedomStudio project (provided by Dornerworks - thanks). Richard Barry 2019-02-11 19:44:13 +00:00
• fb73829148 Ensure eTaskGetState() is brought in automatically if INCLUDE_xTaskAbortDelay is set to 1, as it is a dependency of eTaskGetState(). Added the portTASK_FUNCTION_PROTO macros around the timer task, as the macros are already used by the idle task. Add a PDF of the RISC-V documentation into the repo as the web page is not yet live. Richard Barry 2019-02-08 01:18:08 +00:00
• df5952f655 Add xTaskGetIdleRunTimeCounter() API function to return the run time stats counter for the idle task - useful for POSIX time implementations. Richard Barry 2019-01-21 23:39:48 +00:00
• 817783d75c Copyright updates from Cadence. Gaurav Aggarwal 2019-01-16 19:01:25 +00:00
• a4941ac5db Update main.c() for the WIN32-MingW project so the trace recorder is initialized even when the simple blinky demo is used - otherwise the trace recorder causes an exception as it is used without first being initialized. Richard Barry 2019-01-07 19:40:13 +00:00
• 80df5cd517 Update the pin mux setup on the Vega board demo to enable the LED. Richard Barry 2018-12-31 20:14:34 +00:00
• 11d9c440b8 Move the 'generic' version of freertos_risc_v_chip_specific_extensions.h back to a sub-directory as having it in the RISC-V port's base directory was causing SoftConsole to pick up the wrong version (for an unknown reason). Add a project for the Vega board's RI5CY core. Richard Barry 2018-12-31 18:19:52 +00:00
• e2af102c80 Re-org of RISC-V file structure and naming step 2. Richard Barry 2018-12-30 23:53:47 +00:00
• 818eeccc0c Re-org of RISC-V file structure and naming step 1. Richard Barry 2018-12-30 23:20:26 +00:00
• 3474e750fa Create folder to hold RISC-V chip specific extensions. Richard Barry 2018-12-30 23:15:37 +00:00
• db750d0c82 Update RSIC-V port layer after testing saving and receiving of chip specific registers. Richard Barry 2018-12-30 23:11:40 +00:00
• 60b133b2c6 Move the RISC-V pxPortInitialiseStack() implementation to the assembly port file from the C port file so it can have access to the number of chip specific registers it needs to save space for on the stack. Richard Barry 2018-12-30 20:00:43 +00:00
• 911a1de273 Correct accidental deletion in GenQTest.c. Richard Barry 2018-12-28 03:38:27 +00:00
• d369110167 Allow the size of the stack used by many of the standard demo/test tasks to be overridden by FreeRTOSConfig.h settings. Update the Freedom Studio RISC-V project so the 'full' build configuration is now functional. Richard Barry 2018-12-28 00:44:18 +00:00
• 178fe4f143 Update the Freedom Studio RISC-V project so the gdbinit options are now specified on the command line. Richard Barry 2018-12-27 04:57:49 +00:00
• e5daf23d75 Update Freedom Studio RISC-V demo for the latest GCC RISC-V port - not yet tested. Richard Barry 2018-12-27 04:34:08 +00:00
• 80f6f3e59b Retarget Softconsole RISC-V demo from IGLOO2 to Renode as it can have more RAM and therefore have more test tasks running. Richard Barry 2018-12-24 17:48:10 +00:00
• ce36928ea8 Rename directories in the RISC-V port. Richard Barry 2018-12-24 17:37:02 +00:00
• 2181c0375e Backup Microsemi Renode project before adding a build configuration for the target hardware. Richard Barry 2018-12-19 02:56:13 +00:00
• 8d213b42f2 Add vTimerSetReloadMode() calls to the code coverage tests. Richard Barry 2018-12-17 23:19:23 +00:00
• 6edabbe7ea Update the the MPU simulator project to exercise the timer API. Richard Barry 2018-12-17 22:06:58 +00:00
• 148f588f56 Remove "FromISR' functions from the list of functions that switch to a privileged mode as IRQs are privileged already. Add the vTimerSetReloadMode() API function. Richard Barry 2018-12-17 22:04:18 +00:00
• 8285ca6b5f Update RISC-V_IGLOO2_Creative_SoftConsole demo to make use of new RISC-V porting layer structure and exercise some external interrupts - all tests currently passing in Renode. Richard Barry 2018-12-17 00:01:36 +00:00
• 101806906d Rework RISC-V portASM.S to make it easier to add in chip specific RISC-V extensions and accommodate chips that don't include the CLINT. Richard Barry 2018-12-16 23:59:49 +00:00
• 7cc42b2ab6 Save changes to the RISC-V port layer before making changes necessary to support pulpino too: + Switch positions of the asm functions used to start the kernel and handle traps to enable one to reference to the other. + Handle external interrupts (working with Renode emulator). + The _sp linker variable is now called __freertos_irq_stack_top. Richard Barry 2018-12-16 20:21:29 +00:00
• 866635d2ad Microsemi RISC-V project: Reorganize project to separate Microsemi code into its own directory. Add many more demo and tests. Richard Barry 2018-12-10 20:55:32 +00:00
• 6b37800ade Backup checkin of MiFive demo running in ReNode emulator. Richard Barry 2018-12-10 05:28:05 +00:00
• 9a136a52df Backup check in of the Microsemi IGLOO2 Creative Board RISC-V demo - still a work in progress. Richard Barry 2018-12-04 01:27:06 +00:00
• 4b9dd38d1c Backup checking of the Freedom Studio RISC-V project - still a work in progress. Richard Barry 2018-12-04 01:25:53 +00:00
• 65f7a2dc19 Update RISC-V port to use a separate interrupt stack. Richard Barry 2018-12-04 01:23:41 +00:00
• e85ea96f78 Some efficiency improvements in Risc-V port. Richard Barry 2018-11-28 19:35:40 +00:00
• dc99300fa9 First task running in RISC-V-Qemu-sifive_e-FreedomStudio demo. Richard Barry 2018-11-24 20:59:07 +00:00
• d0ef322b13 Add kernel code to the RISC-V-Qemu-sifive_e-FreedomStudio demo. Richard Barry 2018-11-24 04:42:20 +00:00
• f7102f2342 Add a starting point for a Freedom Studio Risc V project. Richard Barry 2018-11-24 03:48:55 +00:00
• db64297487 Provide each Risc V task with an initial mstatus register value. Richard Barry 2018-11-20 20:12:35 +00:00
• 8cef339aec Update Risc-V port to use environment call in place of software interrupt - still very much a work in progress. Richard Barry 2018-11-19 06:01:29 +00:00
• baee711cb6 Continue work on Risc V port. Richard Barry 2018-11-06 02:04:28 +00:00
• 74d0d16aab Update xTaskRemoveFromEventList() so when tickless idle is used prvResetNextTaskUnblockTime() only gets called if the scheduler is not locked, as it would get called when the scheduler is unlocked in any case. Richard Barry 2018-11-05 19:35:54 +00:00
• 55ff89373a Update the method used to detect if a timer is active. Previously the timer was deemed to be inactive if it was not referenced from a list. However, when a timer is updated it is temporarily removed from, then re-added to a list, so now the timer's active status is stored separately. Richard Barry 2018-10-24 21:37:59 +00:00
• 6fab2b9e0d Add xTaskGetApplicationTaskTagFromISR(), which is an interrupt safe version of xTaskGetApplicationTaskTagFrom(). Richard Barry 2018-10-08 15:10:18 +00:00
• 1af80854e6 Fix Xtensa project file and some documentation improvements. Gaurav Aggarwal 2018-10-02 23:54:51 +00:00
• c6de0001fa Added uxTaskGetStackHighWaterMark2(), which is the same as uxTaskGetStackHighWaterMark() other than the return type. Allows the task name parameter passed into xTaskCreate() to be NULL. Richard Barry 2018-09-30 21:50:05 +00:00
• e3dc5e934b RISC-V tasks now context switching to each other using taskYIELD() - not fully tested yet. Richard Barry 2018-09-27 17:25:17 +00:00
• 2bcb1ab02b Add trap handler to RISC-V port so there is no dependency on third party code. Richard Barry 2018-09-23 03:52:23 +00:00
• 32f35e9130 RISC-V: Added code to setup the timer interrupt - not tested yet. Added the taskYIELD() implementation - so far just checked it generates an interrupt. Richard Barry 2018-09-12 16:33:05 +00:00
• b11eb3a59c RISC-V work in progress: + Initialise task stack. + Successfully jump to start of first task. Richard Barry 2018-09-10 20:50:05 +00:00
• d6c89bb3a0 V10.1.1 Richard Barry 2018-09-07 23:46:52 +00:00
• 3070037cbf Richard Barry 2018-09-07 23:43:39 +00:00
• 0c0f0d0f8f Minor synching - no functional changes. Richard Barry 2018-09-07 22:24:51 +00:00
• ab49c6ae04 Very minor formatting changes, and remove legacy link to V8 upgrade information. Richard Barry 2018-09-07 21:35:05 +00:00
• 92ae8e7aff Update version numbers ready for release. Richard Barry 2018-09-07 18:13:20 +00:00
• 1a235efd2b Update trace configuration files for the updated trace recorder code. Richard Barry 2018-09-06 18:52:45 +00:00
• be9c0730c3 Update trace recorder code to the latest. Some minor changes to enable the configREMOVE_STATIC_QUALIFIER constant to be used by those debuggers that cannot cope with statics being used. Richard Barry 2018-09-06 03:23:03 +00:00
• 21a8ff35dd Two minor updates in the comments to fix html formatting that was preventing doxygen creating documents correctly. Richard Barry 2018-09-01 02:42:34 +00:00
• 97a686b2e1 Fix mixed tabs and spaces in the latest TCP patches. Richard Barry 2018-08-30 18:25:53 +00:00
• e2750cd388 Case unused return values for memset and memcpy to void in stream_buffer.c to avoid compiler warnings when the warning level is turned up. Remove duplicate comment in heap_1.c. Richard Barry 2018-08-29 15:43:41 +00:00
• 0d6e3df7ec Minor updates to fix issues with the Segger kernel aware plug since V10.1.0. Richard Barry 2018-08-28 18:10:42 +00:00
• 9bda04b472 Fix build issues in the FreeRTOS_Plus_TCP_Minimal_Windows_Simulator project: + Set configENABLE_BACKWARD_COMPATIBILITY to 1 in FreeRTOSConfig.h to account for the fact that a member of the List_t structure has been renamed. + Provide a dummy implementation of ulApplicationGetNextSequenceNumber() to prevent linker warnings. Richard Barry 2018-08-28 16:58:21 +00:00
• 893db45834 Changes required for the IAR StateViewer plug-in to work with FreeRTOS V10.1.0. Richard Barry 2018-08-27 23:11:28 +00:00
• b0ce1f61c9 Move some variables from function scope back to being file scope for the benefit of some kernel aware debuggers that were left working in a non-functioning mode after the V10.1.0 release - not last change for this purpose. Richard Barry 2018-08-27 21:59:26 +00:00
• 1068b3c08c V10.1.0 Richard Barry 2018-08-23 00:27:30 +00:00
• a11b1a494d FreeRTOS+UDP was removed in FreeRTOS V10.1.0 as it was replaced by FreeRTOS+TCP, which was brought into the main download in FreeRTOS V10.0.0. FreeRTOS+TCP can be configured as a UDP only stack, and FreeRTOS+UDP does not contain the patches applied to FreeRTOS+TCP. Richard Barry 2018-08-23 00:00:20 +00:00
• 3a1631fda3 Update copyright date ready for tagging V10.1.0. Richard Barry 2018-08-22 23:23:03 +00:00
• bdb088e66f Fix some build issues in older kernel demo projects. Richard Barry 2018-08-22 21:29:21 +00:00