mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-11-04 11:09:01 +01:00
390 lines
15 KiB
C
390 lines
15 KiB
C
/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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#ifndef PORTMACRO_H
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#define PORTMACRO_H
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/* *INDENT-OFF* */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* *INDENT-ON* */
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/*------------------------------------------------------------------------------
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* Port specific definitions.
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*
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* The settings in this file configure FreeRTOS correctly for the given hardware
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* and compiler.
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*
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* These settings should not be altered.
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*------------------------------------------------------------------------------
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*/
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#ifndef configENABLE_MPU
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#error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
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#endif /* configENABLE_MPU */
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/*-----------------------------------------------------------*/
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/**
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* @brief Type definitions.
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*/
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#define portCHAR char
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#define portFLOAT float
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#define portDOUBLE double
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#define portLONG long
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#define portSHORT short
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#define portSTACK_TYPE uint32_t
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#define portBASE_TYPE long
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typedef portSTACK_TYPE StackType_t;
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typedef long BaseType_t;
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typedef unsigned long UBaseType_t;
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#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
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typedef uint16_t TickType_t;
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#define portMAX_DELAY ( TickType_t ) 0xffff
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#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
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typedef uint32_t TickType_t;
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#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
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/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
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* not need to be guarded with a critical section. */
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#define portTICK_TYPE_IS_ATOMIC 1
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#else
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#error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
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#endif
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/*-----------------------------------------------------------*/
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/**
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* Architecture specifics.
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*/
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#define portARCH_NAME "Cortex-M0+"
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#define portSTACK_GROWTH ( -1 )
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#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
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#define portBYTE_ALIGNMENT 8
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#define portNOP()
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#define portINLINE __inline
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#ifndef portFORCE_INLINE
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#define portFORCE_INLINE inline __attribute__( ( always_inline ) )
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#endif
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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/**
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* @brief Extern declarations.
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*/
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extern BaseType_t xPortIsInsideInterrupt( void );
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extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
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extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
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extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
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extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
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extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
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#if ( configENABLE_MPU == 1 )
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extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
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extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
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#endif /* configENABLE_MPU */
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/*-----------------------------------------------------------*/
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/**
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* @brief MPU specific constants.
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*/
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#if ( configENABLE_MPU == 1 )
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#define portUSING_MPU_WRAPPERS 1
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#define portPRIVILEGE_BIT ( 0x80000000UL )
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#else
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#define portPRIVILEGE_BIT ( 0x0UL )
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#endif /* configENABLE_MPU */
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/* Shareable (S), Cacheable (C) and Bufferable (B) bits for flash region. */
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#ifndef configS_C_B_FLASH
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#define configS_C_B_FLASH ( 0x07UL )
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#endif
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/* Shareable (S), Cacheable (C) and Bufferable (B) bits for RAM region. */
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#ifndef configS_C_B_SRAM
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#define configS_C_B_SRAM ( 0x07UL )
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#endif
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/* MPU regions. */
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#define portPRIVILEGED_RAM_REGION ( 7UL )
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#define portPRIVILEGED_FLASH_REGION ( 6UL )
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#define portUNPRIVILEGED_FLASH_REGION ( 5UL )
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#define portSTACK_REGION ( 4UL )
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#define portFIRST_CONFIGURABLE_REGION ( 0UL )
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#define portLAST_CONFIGURABLE_REGION ( 3UL )
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#define portNUM_CONFIGURABLE_REGIONS ( 4UL )
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#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1UL ) /* Plus one to make space for the stack region. */
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/* MPU region sizes. This information is encoded in the SIZE bits of the MPU
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* Region Attribute and Size Register (RASR). */
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#define portMPU_REGION_SIZE_256B ( 0x07UL << 1UL )
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#define portMPU_REGION_SIZE_512B ( 0x08UL << 1UL )
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#define portMPU_REGION_SIZE_1KB ( 0x09UL << 1UL )
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#define portMPU_REGION_SIZE_2KB ( 0x0AUL << 1UL )
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#define portMPU_REGION_SIZE_4KB ( 0x0BUL << 1UL )
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#define portMPU_REGION_SIZE_8KB ( 0x0CUL << 1UL )
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#define portMPU_REGION_SIZE_16KB ( 0x0DUL << 1UL )
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#define portMPU_REGION_SIZE_32KB ( 0x0EUL << 1UL )
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#define portMPU_REGION_SIZE_64KB ( 0x0FUL << 1UL )
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#define portMPU_REGION_SIZE_128KB ( 0x10UL << 1UL )
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#define portMPU_REGION_SIZE_256KB ( 0x11UL << 1UL )
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#define portMPU_REGION_SIZE_512KB ( 0x12UL << 1UL )
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#define portMPU_REGION_SIZE_1MB ( 0x13UL << 1UL )
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#define portMPU_REGION_SIZE_2MB ( 0x14UL << 1UL )
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#define portMPU_REGION_SIZE_4MB ( 0x15UL << 1UL )
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#define portMPU_REGION_SIZE_8MB ( 0x16UL << 1UL )
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#define portMPU_REGION_SIZE_16MB ( 0x17UL << 1UL )
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#define portMPU_REGION_SIZE_32MB ( 0x18UL << 1UL )
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#define portMPU_REGION_SIZE_64MB ( 0x19UL << 1UL )
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#define portMPU_REGION_SIZE_128MB ( 0x1AUL << 1UL )
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#define portMPU_REGION_SIZE_256MB ( 0x1BUL << 1UL )
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#define portMPU_REGION_SIZE_512MB ( 0x1CUL << 1UL )
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#define portMPU_REGION_SIZE_1GB ( 0x1DUL << 1UL )
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#define portMPU_REGION_SIZE_2GB ( 0x1EUL << 1UL )
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#define portMPU_REGION_SIZE_4GB ( 0x1FUL << 1UL )
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/* MPU memory types. This information is encoded in the S ( Shareable), C
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* (Cacheable) and B (Bufferable) bits of the MPU Region Attribute and Size
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* Register (RASR). */
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#define portMPU_REGION_STRONGLY_ORDERED_SHAREABLE ( 0x0UL << 16UL ) /* S=NA, C=0, B=0. */
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#define portMPU_REGION_DEVICE_SHAREABLE ( 0x1UL << 16UL ) /* S=NA, C=0, B=1. */
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#define portMPU_REGION_NORMAL_OIWTNOWA_NONSHARED ( 0x2UL << 16UL ) /* S=0, C=1, B=0. */
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#define portMPU_REGION_NORMAL_OIWTNOWA_SHARED ( 0x6UL << 16UL ) /* S=1, C=1, B=0. */
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#define portMPU_REGION_NORMAL_OIWBNOWA_NONSHARED ( 0x3UL << 16UL ) /* S=0, C=1, B=1.*/
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#define portMPU_REGION_NORMAL_OIWBNOWA_SHARED ( 0x7UL << 16UL ) /* S=1, C=1, B=1.*/
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/* MPU access permissions. This information is encoded in the AP and XN bits of
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* the MPU Region Attribute and Size Register (RASR). */
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#define portMPU_REGION_PRIV_NA_UNPRIV_NA ( 0x0UL << 24UL )
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#define portMPU_REGION_PRIV_RW_UNPRIV_NA ( 0x1UL << 24UL )
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#define portMPU_REGION_PRIV_RW_UNPRIV_RO ( 0x2UL << 24UL )
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#define portMPU_REGION_PRIV_RW_UNPRIV_RW ( 0x3UL << 24UL )
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#define portMPU_REGION_PRIV_RO_UNPRIV_NA ( 0x5UL << 24UL )
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#define portMPU_REGION_PRIV_RO_UNPRIV_RO ( 0x6UL << 24UL )
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#define portMPU_REGION_EXECUTE_NEVER ( 0x1UL << 28UL )
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#if ( configENABLE_MPU == 1 )
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/**
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* @brief Settings to define an MPU region.
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*/
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typedef struct MPURegionSettings
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{
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uint32_t ulRBAR; /**< MPU Region Base Address Register (RBAR) for the region. */
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uint32_t ulRASR; /**< MPU Region Attribute and Size Register (RASR) for the region. */
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} MPURegionSettings_t;
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#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
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#ifndef configSYSTEM_CALL_STACK_SIZE
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#error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
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#endif
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/**
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* @brief System call stack.
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*/
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typedef struct SYSTEM_CALL_STACK_INFO
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{
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uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
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uint32_t * pulSystemCallStack;
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uint32_t * pulTaskStack;
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uint32_t ulLinkRegisterAtSystemCallEntry;
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} xSYSTEM_CALL_STACK_INFO;
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#endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
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/**
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* @brief MPU settings as stored in the TCB.
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*/
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/*
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* +----------+-----------------+---------------+-----+
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* | r4-r11 | r0-r3, r12, LR, | PSP, CONTROL | |
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* | | PC, xPSR | EXC_RETURN | |
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* +----------+-----------------+---------------+-----+
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*
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* <---------><----------------><---------------><---->
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* 8 8 3 1
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*/
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#define CONTEXT_SIZE 20
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/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
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#define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
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#define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
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/* Size of an Access Control List (ACL) entry in bits. */
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#define portACL_ENTRY_SIZE_BITS ( 32U )
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typedef struct MPU_SETTINGS
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{
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MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
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uint32_t ulContext[ CONTEXT_SIZE ];
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uint32_t ulTaskFlags;
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#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
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xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
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#if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
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uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
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#endif
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#endif
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} xMPU_SETTINGS;
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#endif /* configENABLE_MPU == 1 */
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/*-----------------------------------------------------------*/
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/**
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* @brief SVC numbers.
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*/
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#define portSVC_START_SCHEDULER 100
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#define portSVC_RAISE_PRIVILEGE 101
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#define portSVC_SYSTEM_CALL_EXIT 102
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#define portSVC_YIELD 103
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/*-----------------------------------------------------------*/
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/**
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* @brief Scheduler utilities.
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*/
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#if ( configENABLE_MPU == 1 )
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#define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
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#define portYIELD_WITHIN_API() vPortYield()
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#else
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#define portYIELD() vPortYield()
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#define portYIELD_WITHIN_API() vPortYield()
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#endif
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#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
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#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
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#define portEND_SWITCHING_ISR( xSwitchRequired ) \
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do \
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{ \
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if( xSwitchRequired ) \
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{ \
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traceISR_EXIT_TO_SCHEDULER(); \
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portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
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} \
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else \
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{ \
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traceISR_EXIT(); \
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} \
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} while( 0 )
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#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
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/*-----------------------------------------------------------*/
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/**
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* @brief Critical section management.
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*/
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#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask()
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#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x )
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#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
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#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
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#define portENTER_CRITICAL() vPortEnterCritical()
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#define portEXIT_CRITICAL() vPortExitCritical()
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/*-----------------------------------------------------------*/
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/**
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* @brief Tickless idle/low power functionality.
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*/
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#ifndef portSUPPRESS_TICKS_AND_SLEEP
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extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
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#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
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#endif
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/*-----------------------------------------------------------*/
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/**
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* @brief Task function macros as described on the FreeRTOS.org website.
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*/
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#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
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#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
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/*-----------------------------------------------------------*/
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#if ( configENABLE_MPU == 1 )
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/**
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* @brief Checks whether or not the processor is privileged.
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*
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* @return 1 if the processor is already privileged, 0 otherwise.
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*/
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#define portIS_PRIVILEGED() xIsPrivileged()
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/**
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* @brief Raise an SVC request to raise privilege.
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*
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* The SVC handler checks that the SVC was raised from a system call and only
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* then it raises the privilege. If this is called from any other place,
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* the privilege is not raised.
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*/
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#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
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/**
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* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
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* register.
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*/
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#define portRESET_PRIVILEGE() vResetPrivilege()
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#else
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#define portIS_PRIVILEGED()
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#define portRAISE_PRIVILEGE()
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#define portRESET_PRIVILEGE()
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#endif /* configENABLE_MPU */
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/*-----------------------------------------------------------*/
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#if ( configENABLE_MPU == 1 )
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extern BaseType_t xPortIsTaskPrivileged( void );
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/**
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* @brief Checks whether or not the calling task is privileged.
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*
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* @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
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*/
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#define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
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#endif /* configENABLE_MPU == 1 */
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/*-----------------------------------------------------------*/
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/**
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* @brief Barriers.
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*/
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#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
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/*-----------------------------------------------------------*/
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/* *INDENT-OFF* */
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#ifdef __cplusplus
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}
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#endif
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/* *INDENT-ON* */
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#endif /* PORTMACRO_H */
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