mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-11-04 11:09:01 +01:00
526 lines
28 KiB
ArmAsm
526 lines
28 KiB
ArmAsm
/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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/* Including FreeRTOSConfig.h here will cause build errors if the header file
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contains code not understood by the assembler - for example the 'extern' keyword.
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To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
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the code is included in C files but excluded by the preprocessor in assembly
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files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
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#include "FreeRTOSConfig.h"
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/* System call numbers includes. */
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#include "mpu_syscall_numbers.h"
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#ifndef configUSE_MPU_WRAPPERS_V1
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#define configUSE_MPU_WRAPPERS_V1 0
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#endif
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EXTERN pxCurrentTCB
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EXTERN xSecureContext
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EXTERN vTaskSwitchContext
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EXTERN vPortSVCHandler_C
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EXTERN SecureContext_SaveContext
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EXTERN SecureContext_LoadContext
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#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
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EXTERN vSystemCallEnter
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EXTERN vSystemCallExit
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#endif
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PUBLIC xIsPrivileged
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PUBLIC vResetPrivilege
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PUBLIC vPortAllocateSecureContext
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PUBLIC vRestoreContextOfFirstTask
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PUBLIC vRaisePrivilege
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PUBLIC vStartFirstTask
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PUBLIC ulSetInterruptMask
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PUBLIC vClearInterruptMask
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PUBLIC PendSV_Handler
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PUBLIC SVC_Handler
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PUBLIC vPortFreeSecureContext
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#if ( configENABLE_FPU == 1 )
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#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
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#endif
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/*-----------------------------------------------------------*/
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/*---------------- Unprivileged Functions -------------------*/
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/*-----------------------------------------------------------*/
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SECTION .text:CODE:NOROOT(2)
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THUMB
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/*-----------------------------------------------------------*/
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xIsPrivileged:
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mrs r0, control /* r0 = CONTROL. */
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movs r1, #1 /* r1 = 1. */
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tst r0, r1 /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
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beq running_privileged /* If the result of previous AND operation was 0, branch. */
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movs r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
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bx lr /* Return. */
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running_privileged:
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movs r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
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bx lr /* Return. */
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/*-----------------------------------------------------------*/
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vResetPrivilege:
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mrs r0, control /* r0 = CONTROL. */
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movs r1, #1 /* r1 = 1. */
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orrs r0, r1 /* r0 = r0 | r1. */
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msr control, r0 /* CONTROL = r0. */
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bx lr /* Return to the caller. */
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/*-----------------------------------------------------------*/
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vPortAllocateSecureContext:
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svc 100 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 100. */
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bx lr /* Return. */
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/*-----------------------------------------------------------*/
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/*----------------- Privileged Functions --------------------*/
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/*-----------------------------------------------------------*/
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SECTION privileged_functions:CODE:NOROOT(2)
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THUMB
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/*-----------------------------------------------------------*/
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#if ( configENABLE_MPU == 1 )
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vRestoreContextOfFirstTask:
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program_mpu_first_task:
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ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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ldr r0, [r3] /* r0 = pxCurrentTCB.*/
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dmb /* Complete outstanding transfers before disabling MPU. */
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ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
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ldr r2, [r1] /* Read the value of MPU_CTRL. */
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movs r3, #1 /* r3 = 1. */
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bics r2, r3 /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
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str r2, [r1] /* Disable MPU. */
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adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
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ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
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ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
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str r1, [r2] /* Program MAIR0. */
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adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
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ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
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movs r3, #4 /* r3 = 4. */
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str r3, [r1] /* Program RNR = 4. */
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ldmia r0!, {r4-r5} /* Read first set of RBAR/RLAR registers from TCB. */
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ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
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stmia r2!, {r4-r5} /* Write first set of RBAR/RLAR registers. */
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movs r3, #5 /* r3 = 5. */
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str r3, [r1] /* Program RNR = 5. */
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ldmia r0!, {r4-r5} /* Read second set of RBAR/RLAR registers from TCB. */
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ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
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stmia r2!, {r4-r5} /* Write second set of RBAR/RLAR registers. */
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movs r3, #6 /* r3 = 6. */
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str r3, [r1] /* Program RNR = 6. */
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ldmia r0!, {r4-r5} /* Read third set of RBAR/RLAR registers from TCB. */
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ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
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stmia r2!, {r4-r5} /* Write third set of RBAR/RLAR registers. */
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movs r3, #7 /* r3 = 6. */
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str r3, [r1] /* Program RNR = 7. */
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ldmia r0!, {r4-r5} /* Read fourth set of RBAR/RLAR registers from TCB. */
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ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
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stmia r2!, {r4-r5} /* Write fourth set of RBAR/RLAR registers. */
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ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
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ldr r2, [r1] /* Read the value of MPU_CTRL. */
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movs r3, #1 /* r3 = 1. */
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orrs r2, r3 /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
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str r2, [r1] /* Enable MPU. */
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dsb /* Force memory writes before continuing. */
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restore_context_first_task:
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ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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ldr r1, [r3] /* r1 = pxCurrentTCB.*/
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ldr r2, [r1] /* r2 = Location of saved context in TCB. */
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restore_special_regs_first_task:
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subs r2, #20
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ldmia r2!, {r0, r3-r6} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
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subs r2, #20
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msr psp, r3
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msr control, r5
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mov lr, r6
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ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
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str r0, [r4] /* Restore xSecureContext. */
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restore_general_regs_first_task:
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subs r2, #32
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ldmia r2!, {r4-r7} /* r4-r7 contain half of the hardware saved context. */
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stmia r3!, {r4-r7} /* Copy half of the the hardware saved context on the task stack. */
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ldmia r2!, {r4-r7} /* r4-r7 contain rest half of the hardware saved context. */
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stmia r3!, {r4-r7} /* Copy rest half of the the hardware saved context on the task stack. */
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subs r2, #48
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ldmia r2!, {r4-r7} /* Restore r8-r11. */
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mov r8, r4 /* r8 = r4. */
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mov r9, r5 /* r9 = r5. */
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mov r10, r6 /* r10 = r6. */
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mov r11, r7 /* r11 = r7. */
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subs r2, #32
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ldmia r2!, {r4-r7} /* Restore r4-r7. */
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subs r2, #16
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restore_context_done_first_task:
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str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */
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bx lr
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#else /* configENABLE_MPU */
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vRestoreContextOfFirstTask:
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ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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ldr r3, [r2] /* Read pxCurrentTCB. */
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ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
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ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
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ldr r4, =xSecureContext
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str r1, [r4] /* Set xSecureContext to this task's value for the same. */
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movs r1, #2 /* r1 = 2. */
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msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
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adds r0, #32 /* Discard everything up to r0. */
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msr psp, r0 /* This is now the new top of stack to use in the task. */
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isb
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bx r3 /* Finally, branch to EXC_RETURN. */
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#endif /* configENABLE_MPU */
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/*-----------------------------------------------------------*/
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vRaisePrivilege:
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mrs r0, control /* Read the CONTROL register. */
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movs r1, #1 /* r1 = 1. */
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bics r0, r1 /* Clear the bit 0. */
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msr control, r0 /* Write back the new CONTROL value. */
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bx lr /* Return to the caller. */
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/*-----------------------------------------------------------*/
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vStartFirstTask:
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ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */
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ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */
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ldr r0, [r0] /* The first entry in vector table is stack pointer. */
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msr msp, r0 /* Set the MSP back to the start of the stack. */
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cpsie i /* Globally enable interrupts. */
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dsb
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isb
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svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
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/*-----------------------------------------------------------*/
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ulSetInterruptMask:
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mrs r0, PRIMASK
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cpsid i
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bx lr
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/*-----------------------------------------------------------*/
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vClearInterruptMask:
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msr PRIMASK, r0
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bx lr
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/*-----------------------------------------------------------*/
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#if ( configENABLE_MPU == 1 )
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PendSV_Handler:
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ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
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ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
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ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/
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ldr r2, [r1] /* r2 = Location in TCB where the context should be saved. */
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cbz r0, save_ns_context /* No secure context to save. */
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save_s_context:
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push {r0-r2, lr}
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bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
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pop {r0-r3} /* LR is now in r3. */
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mov lr, r3 /* Restore LR. */
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save_ns_context:
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mov r3, lr /* r3 = LR (EXC_RETURN). */
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lsls r3, r3, #25 /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
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bmi save_special_regs /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
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save_general_regs:
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mrs r3, psp
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stmia r2!, {r4-r7} /* Store r4-r7. */
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mov r4, r8 /* r4 = r8. */
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mov r5, r9 /* r5 = r9. */
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mov r6, r10 /* r6 = r10. */
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mov r7, r11 /* r7 = r11. */
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stmia r2!, {r4-r7} /* Store r8-r11. */
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ldmia r3!, {r4-r7} /* Copy half of the hardware saved context into r4-r7. */
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stmia r2!, {r4-r7} /* Store the hardware saved context. */
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ldmia r3!, {r4-r7} /* Copy rest half of the hardware saved context into r4-r7. */
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stmia r2!, {r4-r7} /* Store the hardware saved context. */
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save_special_regs:
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mrs r3, psp /* r3 = PSP. */
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movs r4, #0 /* r4 = 0. 0 is stored in the PSPLIM slot. */
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mrs r5, control /* r5 = CONTROL. */
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mov r6, lr /* r6 = LR. */
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stmia r2!, {r0, r3-r6} /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
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str r2, [r1] /* Save the location from where the context should be restored as the first member of TCB. */
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select_next_task:
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cpsid i
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bl vTaskSwitchContext
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cpsie i
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program_mpu:
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ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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ldr r0, [r3] /* r0 = pxCurrentTCB.*/
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dmb /* Complete outstanding transfers before disabling MPU. */
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ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
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ldr r2, [r1] /* Read the value of MPU_CTRL. */
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movs r3, #1 /* r3 = 1. */
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bics r2, r3 /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
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str r2, [r1] /* Disable MPU. */
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adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
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ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
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ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
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str r1, [r2] /* Program MAIR0. */
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adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
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ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
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movs r3, #4 /* r3 = 4. */
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str r3, [r1] /* Program RNR = 4. */
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ldmia r0!, {r4-r5} /* Read first set of RBAR/RLAR registers from TCB. */
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ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
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stmia r2!, {r4-r5} /* Write first set of RBAR/RLAR registers. */
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movs r3, #5 /* r3 = 5. */
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str r3, [r1] /* Program RNR = 5. */
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ldmia r0!, {r4-r5} /* Read second set of RBAR/RLAR registers from TCB. */
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ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
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stmia r2!, {r4-r5} /* Write second set of RBAR/RLAR registers. */
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movs r3, #6 /* r3 = 6. */
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str r3, [r1] /* Program RNR = 6. */
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ldmia r0!, {r4-r5} /* Read third set of RBAR/RLAR registers from TCB. */
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ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
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stmia r2!, {r4-r5} /* Write third set of RBAR/RLAR registers. */
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movs r3, #7 /* r3 = 6. */
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str r3, [r1] /* Program RNR = 7. */
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ldmia r0!, {r4-r5} /* Read fourth set of RBAR/RLAR registers from TCB. */
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ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
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stmia r2!, {r4-r5} /* Write fourth set of RBAR/RLAR registers. */
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ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
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ldr r2, [r1] /* Read the value of MPU_CTRL. */
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movs r3, #1 /* r3 = 1. */
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orrs r2, r3 /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
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str r2, [r1] /* Enable MPU. */
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dsb /* Force memory writes before continuing. */
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restore_context:
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ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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ldr r1, [r3] /* r1 = pxCurrentTCB.*/
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ldr r2, [r1] /* r2 = Location of saved context in TCB. */
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restore_special_regs:
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subs r2, #20
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ldmia r2!, {r0, r3-r6} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
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subs r2, #20
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msr psp, r3
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msr control, r5
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mov lr, r6
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ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
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str r0, [r4] /* Restore xSecureContext. */
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cbz r0, restore_ns_context /* No secure context to restore. */
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restore_s_context:
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push {r1-r3, lr}
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bl SecureContext_LoadContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
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pop {r1-r4} /* LR is now in r4. */
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mov lr, r4
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restore_ns_context:
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mov r0, lr /* r0 = LR (EXC_RETURN). */
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lsls r0, r0, #25 /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
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bmi restore_context_done /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
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restore_general_regs:
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subs r2, #32
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ldmia r2!, {r4-r7} /* r4-r7 contain half of the hardware saved context. */
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stmia r3!, {r4-r7} /* Copy half of the the hardware saved context on the task stack. */
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ldmia r2!, {r4-r7} /* r4-r7 contain rest half of the hardware saved context. */
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stmia r3!, {r4-r7} /* Copy rest half of the the hardware saved context on the task stack. */
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subs r2, #48
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ldmia r2!, {r4-r7} /* Restore r8-r11. */
|
|
mov r8, r4 /* r8 = r4. */
|
|
mov r9, r5 /* r9 = r5. */
|
|
mov r10, r6 /* r10 = r6. */
|
|
mov r11, r7 /* r11 = r7. */
|
|
subs r2, #32
|
|
ldmia r2!, {r4-r7} /* Restore r4-r7. */
|
|
subs r2, #16
|
|
|
|
restore_context_done:
|
|
str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */
|
|
bx lr
|
|
|
|
#else /* configENABLE_MPU */
|
|
|
|
PendSV_Handler:
|
|
ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
|
|
ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
|
|
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
|
|
ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
|
|
mrs r2, psp /* Read PSP in r2. */
|
|
|
|
cbz r0, save_ns_context /* No secure context to save. */
|
|
push {r0-r2, r14}
|
|
bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
|
|
pop {r0-r3} /* LR is now in r3. */
|
|
mov lr, r3 /* LR = r3. */
|
|
lsls r1, r3, #25 /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
|
|
bpl save_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
|
|
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
|
|
ldr r1, [r3] /* Read pxCurrentTCB. */
|
|
|
|
subs r2, r2, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */
|
|
str r2, [r1] /* Save the new top of stack in TCB. */
|
|
movs r1, #0 /* r1 = 0. 0 is stored in the PSPLIM slot. */
|
|
mov r3, lr /* r3 = LR/EXC_RETURN. */
|
|
stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
|
|
|
|
b select_next_task
|
|
|
|
save_ns_context:
|
|
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
|
|
ldr r1, [r3] /* Read pxCurrentTCB. */
|
|
subs r2, r2, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
|
|
str r2, [r1] /* Save the new top of stack in TCB. */
|
|
movs r1, #0 /* r1 = 0. 0 is stored in the PSPLIM slot. */
|
|
mov r3, lr /* r3 = LR/EXC_RETURN. */
|
|
stmia r2!, {r0, r1, r3-r7} /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
|
|
mov r4, r8 /* r4 = r8. */
|
|
mov r5, r9 /* r5 = r9. */
|
|
mov r6, r10 /* r6 = r10. */
|
|
mov r7, r11 /* r7 = r11. */
|
|
stmia r2!, {r4-r7} /* Store the high registers that are not saved automatically. */
|
|
|
|
select_next_task:
|
|
cpsid i
|
|
bl vTaskSwitchContext
|
|
cpsie i
|
|
|
|
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
|
|
ldr r1, [r3] /* Read pxCurrentTCB. */
|
|
ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
|
|
|
|
ldmia r2!, {r0, r1, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
|
|
mov lr, r4 /* LR = r4. */
|
|
ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
|
|
str r0, [r3] /* Restore the task's xSecureContext. */
|
|
cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */
|
|
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
|
|
ldr r1, [r3] /* Read pxCurrentTCB. */
|
|
push {r2, r4}
|
|
bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
|
|
pop {r2, r4}
|
|
mov lr, r4 /* LR = r4. */
|
|
lsls r1, r4, #25 /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
|
|
bpl restore_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
|
|
msr psp, r2 /* Remember the new top of stack for the task. */
|
|
bx lr
|
|
|
|
restore_ns_context:
|
|
adds r2, r2, #16 /* Move to the high registers. */
|
|
ldmia r2!, {r4-r7} /* Restore the high registers that are not automatically restored. */
|
|
mov r8, r4 /* r8 = r4. */
|
|
mov r9, r5 /* r9 = r5. */
|
|
mov r10, r6 /* r10 = r6. */
|
|
mov r11, r7 /* r11 = r7. */
|
|
msr psp, r2 /* Remember the new top of stack for the task. */
|
|
subs r2, r2, #32 /* Go back to the low registers. */
|
|
ldmia r2!, {r4-r7} /* Restore the low registers that are not automatically restored. */
|
|
bx lr
|
|
|
|
#endif /* configENABLE_MPU */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
|
|
|
|
SVC_Handler:
|
|
movs r0, #4
|
|
mov r1, lr
|
|
tst r0, r1
|
|
beq stack_on_msp
|
|
stack_on_psp:
|
|
mrs r0, psp
|
|
b route_svc
|
|
stack_on_msp:
|
|
mrs r0, msp
|
|
b route_svc
|
|
|
|
route_svc:
|
|
ldr r3, [r0, #24]
|
|
subs r3, #2
|
|
ldrb r2, [r3, #0]
|
|
cmp r2, #NUM_SYSTEM_CALLS
|
|
blt system_call_enter
|
|
cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */
|
|
beq system_call_exit
|
|
b vPortSVCHandler_C
|
|
|
|
system_call_enter:
|
|
b vSystemCallEnter
|
|
system_call_exit:
|
|
b vSystemCallExit
|
|
|
|
#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
|
|
|
|
SVC_Handler:
|
|
movs r0, #4
|
|
mov r1, lr
|
|
tst r0, r1
|
|
beq stacking_used_msp
|
|
mrs r0, psp
|
|
b vPortSVCHandler_C
|
|
stacking_used_msp:
|
|
mrs r0, msp
|
|
b vPortSVCHandler_C
|
|
|
|
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
vPortFreeSecureContext:
|
|
ldr r2, [r0] /* The first item in the TCB is the top of the stack. */
|
|
ldr r1, [r2] /* The first item on the stack is the task's xSecureContext. */
|
|
cmp r1, #0 /* Raise svc if task's xSecureContext is not NULL. */
|
|
bne free_secure_context /* Branch if r1 != 0. */
|
|
bx lr /* There is no secure context (xSecureContext is NULL). */
|
|
free_secure_context:
|
|
svc 101 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 101. */
|
|
bx lr /* Return. */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
END
|