Saiiijchan
64fd9291ef
RISC-V: refine fpu reg context offset ( #1257 )
...
RISC-V: refine fpu reg context offset
pxCode and mstatus stored at index 0 and 1 are based on XLEN.
Therefore, the correct formula to calculate the FPU register index
should be ( ( 2 * portWORD_SIZE ) + ( regIndex * portFPU_REG_SIZE ) ).
Signed-off-by: wangfei_chen <wangfei_chen@realsil.com.cn>
2025-03-13 21:10:51 +05:30
..
2024-02-26 09:26:42 -08:00
2024-11-01 10:09:49 -07:00
2024-02-26 09:26:42 -08:00
2024-02-26 09:26:42 -08:00
2024-11-04 16:35:52 +05:30
2025-01-22 17:00:50 -08:00
2025-01-13 14:48:10 -08:00
2024-04-08 17:50:55 -07:00
2024-04-08 17:50:55 -07:00
2024-11-01 10:09:49 -07:00
2024-11-04 16:35:52 +05:30
2025-01-25 13:34:03 +05:30
2025-01-25 13:34:03 +05:30
2024-11-04 16:35:52 +05:30
2024-11-04 16:35:52 +05:30
2025-02-24 21:54:15 +05:30
2025-02-24 21:54:15 +05:30
2025-02-24 21:54:15 +05:30
2025-02-24 21:54:15 +05:30
2025-02-24 21:54:15 +05:30
2025-02-24 21:54:15 +05:30
2025-02-24 21:54:15 +05:30
2025-02-24 21:54:15 +05:30
2025-02-24 21:54:15 +05:30
2025-02-24 21:54:15 +05:30
2024-11-04 16:35:52 +05:30
2024-11-01 10:09:49 -07:00
2024-08-08 21:07:11 +05:30
2024-02-26 09:26:42 -08:00
2024-11-01 10:09:49 -07:00
2021-09-14 19:25:46 -07:00
2021-09-14 19:25:46 -07:00
2024-02-26 09:26:42 -08:00
2024-02-26 09:26:42 -08:00
2024-02-26 09:26:42 -08:00
2024-02-26 09:26:42 -08:00
2024-09-09 12:54:38 +05:30
2021-06-30 15:07:55 -07:00
2024-02-26 09:26:42 -08:00
2024-02-26 09:26:42 -08:00
2024-02-26 09:26:42 -08:00
2024-02-26 09:26:42 -08:00
2024-02-26 09:26:42 -08:00
2024-02-26 09:26:42 -08:00
2024-02-26 09:26:42 -08:00
2025-03-13 21:10:51 +05:30
2024-10-15 11:09:45 +05:30
2024-11-04 16:35:52 +05:30
2024-11-04 16:35:52 +05:30
2024-11-04 16:35:52 +05:30
2024-11-04 16:35:52 +05:30
2024-11-04 16:35:52 +05:30
2024-02-26 09:26:42 -08:00
2024-02-26 09:26:42 -08:00