Saiiijchan 64fd9291ef
RISC-V: refine fpu reg context offset (#1257)
RISC-V: refine fpu reg context offset

pxCode and mstatus stored at index 0 and 1 are based on XLEN.
Therefore, the correct formula to calculate the FPU register index
should be ( ( 2 * portWORD_SIZE ) + ( regIndex * portFPU_REG_SIZE ) ).

Signed-off-by: wangfei_chen <wangfei_chen@realsil.com.cn>
2025-03-13 21:10:51 +05:30
..
2024-11-01 10:09:49 -07:00
2024-11-01 10:09:49 -07:00
2024-11-01 10:09:49 -07:00
2024-11-01 10:09:49 -07:00