mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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573 lines
21 KiB
C
573 lines
21 KiB
C
/*
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* SPDX-FileCopyrightText: 2020 Amazon.com, Inc. or its affiliates
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* SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc.
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*
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* SPDX-License-Identifier: MIT
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*
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* SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
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*/
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software. If you wish to use our Amazon
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* FreeRTOS name, please do so in a fair use way that does not cause confusion.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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* 1 tab == 4 spaces!
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*/
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/*
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* Copyright (c) 2015-2019 Cadence Design Systems, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <stdlib.h>
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#include <string.h>
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#include <xtensa/config/core.h>
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#include "xtensa_rtos.h"
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#include "esp_idf_version.h"
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#if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) )
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#include "rom/ets_sys.h"
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#include "esp_panic.h"
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#include "esp_crosscore_int.h"
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#else
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#if CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/rom/ets_sys.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/ets_sys.h"
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#elif CONFIG_IDF_TARGET_ESP32
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#include "esp32/rom/ets_sys.h"
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#endif
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#include "esp_private/panic_reason.h"
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#include "esp_debug_helpers.h"
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#include "esp_private/crosscore_int.h"
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#include "esp_log.h"
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#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */
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#include "soc/cpu.h"
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#include "FreeRTOS.h"
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#include "task.h"
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#include "esp_heap_caps.h"
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#include "esp_intr_alloc.h"
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#include "port_systick.h"
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/* Defined in xtensa_context.S */
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extern void _xt_coproc_init( void );
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_Static_assert( tskNO_AFFINITY == CONFIG_FREERTOS_NO_AFFINITY, "incorrect tskNO_AFFINITY value" );
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/*-----------------------------------------------------------*/
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extern volatile int port_xSchedulerRunning[ portNUM_PROCESSORS ];
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unsigned port_interruptNesting[ portNUM_PROCESSORS ] = { 0 }; /* Interrupt nesting level. Increased/decreased in portasm.c, _frxt_int_enter/_frxt_int_exit */
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/*-----------------------------------------------------------*/
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/* User exception dispatcher when exiting */
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void _xt_user_exit( void );
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#if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER
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/* Wrapper to allow task functions to return (increases stack overhead by 16 bytes) */
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static void vPortTaskWrapper( TaskFunction_t pxCode,
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void * pvParameters )
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{
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pxCode( pvParameters );
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/*FreeRTOS tasks should not return. Log the task name and abort. */
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char * pcTaskName = pcTaskGetTaskName( NULL );
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ESP_LOGE( "FreeRTOS", "FreeRTOS Task \"%s\" should not return, Aborting now!", pcTaskName );
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abort();
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}
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#endif /* if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER */
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/*
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* Stack initialization
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*/
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/* *INDENT-OFF* */
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#if portUSING_MPU_WRAPPERS
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StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
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TaskFunction_t pxCode,
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void * pvParameters,
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BaseType_t xRunPrivileged )
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#else
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StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
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TaskFunction_t pxCode,
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void * pvParameters )
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#endif
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/* *INDENT-ON* */
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{
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StackType_t * sp;
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StackType_t * tp;
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XtExcFrame * frame;
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#if XCHAL_CP_NUM > 0
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uint32_t * p;
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#endif
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uint32_t * threadptr;
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void * task_thread_local_start;
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extern int _thread_local_start, _thread_local_end, _flash_rodata_start, _flash_rodata_align;
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/* TODO: check that TLS area fits the stack */
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uint32_t thread_local_sz = ( uint8_t * ) &_thread_local_end - ( uint8_t * ) &_thread_local_start;
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thread_local_sz = ALIGNUP( 0x10, thread_local_sz );
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/* Initialize task's stack so that we have the following structure at the top:
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*
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* ----LOW ADDRESSES ----------------------------------------HIGH ADDRESSES----------
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* task stack | interrupt stack frame | thread local vars | co-processor save area |
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* ----------------------------------------------------------------------------------
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| |
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| SP pxTopOfStack
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| All parts are aligned to 16 byte boundary.
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*/
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/* Create interrupt stack frame aligned to 16 byte boundary */
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sp = ( StackType_t * ) ( ( ( UBaseType_t ) pxTopOfStack - XT_CP_SIZE - thread_local_sz - XT_STK_FRMSZ ) & ~0xf );
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/* Clear the entire frame (do not use memset() because we don't depend on C library) */
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for( tp = sp; tp <= pxTopOfStack; ++tp )
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{
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*tp = 0;
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}
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frame = ( XtExcFrame * ) sp;
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/* Explicitly initialize certain saved registers */
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#if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER
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frame->pc = ( UBaseType_t ) vPortTaskWrapper; /* task wrapper */
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#else
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frame->pc = ( UBaseType_t ) pxCode; /* task entrypoint */
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#endif
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frame->a0 = 0; /* to terminate GDB backtrace */
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frame->a1 = ( UBaseType_t ) sp + XT_STK_FRMSZ; /* physical top of stack frame */
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frame->exit = ( UBaseType_t ) _xt_user_exit; /* user exception exit dispatcher */
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/* Set initial PS to int level 0, EXCM disabled ('rfe' will enable), user mode. */
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/* Also set entry point argument parameter. */
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#ifdef __XTENSA_CALL0_ABI__
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#if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER
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frame->a2 = ( UBaseType_t ) pxCode;
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frame->a3 = ( UBaseType_t ) pvParameters;
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#else
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frame->a2 = ( UBaseType_t ) pvParameters;
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#endif
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frame->ps = PS_UM | PS_EXCM;
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#else
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/* + for windowed ABI also set WOE and CALLINC (pretend task was 'call4'd). */
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#if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER
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frame->a6 = ( UBaseType_t ) pxCode;
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frame->a7 = ( UBaseType_t ) pvParameters;
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#else
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frame->a6 = ( UBaseType_t ) pvParameters;
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#endif
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frame->ps = PS_UM | PS_EXCM | PS_WOE | PS_CALLINC( 1 );
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#endif /* ifdef __XTENSA_CALL0_ABI__ */
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#ifdef XT_USE_SWPRI
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/* Set the initial virtual priority mask value to all 1's. */
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frame->vpri = 0xFFFFFFFF;
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#endif
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/* Init threadptr register and set up TLS run-time area. */
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task_thread_local_start = ( void * ) ( ( ( uint32_t ) pxTopOfStack - XT_CP_SIZE - thread_local_sz ) & ~0xf );
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memcpy( task_thread_local_start, &_thread_local_start, thread_local_sz );
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threadptr = ( uint32_t * ) ( sp + XT_STK_EXTRA );
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/* Calculate THREADPTR value.
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* The generated code will add THREADPTR value to a constant value determined at link time,
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* to get the address of the TLS variable.
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* The constant value is calculated by the linker as follows
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* (search for 'tpoff' in elf32-xtensa.c in BFD):
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* offset = address - tls_section_vma + align_up(TCB_SIZE, tls_section_alignment)
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* where TCB_SIZE is hardcoded to 8.
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*/
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const uint32_t tls_section_alignment = ( uint32_t ) &_flash_rodata_align; /* ALIGN value of .flash.rodata section */
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const uint32_t tcb_size = 8; /* Unrelated to FreeRTOS, this is the constant from BFD */
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const uint32_t base = ( tcb_size + tls_section_alignment - 1 ) & ( ~( tls_section_alignment - 1 ) );
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*threadptr = ( uint32_t ) task_thread_local_start - ( ( uint32_t ) &_thread_local_start - ( uint32_t ) &_flash_rodata_start ) - base;
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#if XCHAL_CP_NUM > 0
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/* Init the coprocessor save area (see xtensa_context.h) */
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/* No access to TCB here, so derive indirectly. Stack growth is top to bottom.
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* //p = (uint32_t *) xMPUSettings->coproc_area;
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*/
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p = ( uint32_t * ) ( ( ( uint32_t ) pxTopOfStack - XT_CP_SIZE ) & ~0xf );
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configASSERT( ( uint32_t ) p >= frame->a1 );
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p[ 0 ] = 0;
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p[ 1 ] = 0;
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p[ 2 ] = ( ( ( uint32_t ) p ) + 12 + XCHAL_TOTAL_SA_ALIGN - 1 ) & -XCHAL_TOTAL_SA_ALIGN;
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#endif
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return sp;
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}
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/*-----------------------------------------------------------*/
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void vPortEndScheduler( void )
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{
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/* It is unlikely that the Xtensa port will get stopped. If required simply
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* disable the tick interrupt here. */
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abort();
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}
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/*-----------------------------------------------------------*/
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BaseType_t xPortStartScheduler( void )
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{
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portDISABLE_INTERRUPTS();
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/* Interrupts are disabled at this point and stack contains PS with enabled interrupts when task context is restored */
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#if XCHAL_CP_NUM > 0
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/* Initialize co-processor management for tasks. Leave CPENABLE alone. */
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_xt_coproc_init();
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#endif
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/* Setup the hardware to generate the tick */
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vPortSetupTimer();
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/* NOTE: For ESP32-S3, vPortSetupTimer allocates an interrupt for the
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* systimer which is used as the source for FreeRTOS systick.
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*
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* The behaviour of portEXIT_CRITICAL is different in FreeRTOS and ESP-IDF -
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* the former enables the interrupts no matter what the state was at the beginning
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* of the call while the latter restores the interrupt state to what was at the
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* beginning of the call.
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*
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* This resulted in the interrupts being enabled before the _frxt_dispatch call,
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* who was unable to switch context to the queued tasks.
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*/
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portDISABLE_INTERRUPTS();
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port_xSchedulerRunning[ xPortGetCoreID() ] = 1;
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/* Cannot be directly called from C; never returns */
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__asm__ volatile ( "call0 _frxt_dispatch\n" );
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/* Should not get here. */
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return pdTRUE;
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}
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/*-----------------------------------------------------------*/
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void vPortYieldOtherCore( BaseType_t coreid )
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{
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esp_crosscore_int_send_yield( coreid );
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}
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/*-----------------------------------------------------------*/
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/*
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* Used to set coprocessor area in stack. Current hack is to reuse MPU pointer for coprocessor area.
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*/
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#if portUSING_MPU_WRAPPERS
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void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
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const struct xMEMORY_REGION * const xRegions,
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StackType_t * pxBottomOfStack,
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configSTACK_DEPTH_TYPE uxStackDepth )
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{
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#if XCHAL_CP_NUM > 0
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xMPUSettings->coproc_area = ( StackType_t * ) ( ( uint32_t ) ( pxBottomOfStack + uxStackDepth - 1 ) );
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xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) xMPUSettings->coproc_area ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
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xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( uint32_t ) xMPUSettings->coproc_area - XT_CP_SIZE ) & ~0xf );
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/* NOTE: we cannot initialize the coprocessor save area here because FreeRTOS is going to
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* clear the stack area after we return. This is done in pxPortInitialiseStack().
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*/
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#endif
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}
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void vPortReleaseTaskMPUSettings( xMPU_SETTINGS * xMPUSettings )
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{
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/* If task has live floating point registers somewhere, release them */
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_xt_coproc_release( xMPUSettings->coproc_area );
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}
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#endif /* if portUSING_MPU_WRAPPERS */
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/*
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* Returns true if the current core is in ISR context; low prio ISR, med prio ISR or timer tick ISR. High prio ISRs
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* aren't detected here, but they normally cannot call C code, so that should not be an issue anyway.
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*/
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BaseType_t xPortInIsrContext()
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{
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unsigned int irqStatus;
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BaseType_t ret;
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irqStatus = portSET_INTERRUPT_MASK_FROM_ISR();
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ret = ( port_interruptNesting[ xPortGetCoreID() ] != 0 );
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portCLEAR_INTERRUPT_MASK_FROM_ISR( irqStatus );
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return ret;
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}
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/*
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* This function will be called in High prio ISRs. Returns true if the current core was in ISR context
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* before calling into high prio ISR context.
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*/
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BaseType_t IRAM_ATTR xPortInterruptedFromISRContext()
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{
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return( port_interruptNesting[ xPortGetCoreID() ] != 0 );
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}
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void IRAM_ATTR vPortEvaluateYieldFromISR( int argc,
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... )
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{
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BaseType_t xYield;
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va_list ap;
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va_start( ap, argc );
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if( argc )
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{
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xYield = ( BaseType_t ) va_arg( ap, int );
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va_end( ap );
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}
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else
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{
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/*it is a empty parameter vPortYieldFromISR macro call: */
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va_end( ap );
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traceISR_EXIT_TO_SCHEDULER();
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_frxt_setup_switch();
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return;
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}
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/*Yield exists, so need evaluate it first then switch: */
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if( xYield == pdTRUE )
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{
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traceISR_EXIT_TO_SCHEDULER();
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_frxt_setup_switch();
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}
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}
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void vPortAssertIfInISR()
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{
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if( xPortInIsrContext() )
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{
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esp_rom_printf( "core=%d port_interruptNesting=%d\n\n", xPortGetCoreID(), port_interruptNesting[ xPortGetCoreID() ] );
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}
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configASSERT( !xPortInIsrContext() );
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}
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/*
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* For kernel use: Initialize a per-CPU mux. Mux will be initialized unlocked.
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*/
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void vPortCPUInitializeMutex( portMUX_TYPE * mux )
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{
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#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
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esp_rom_printf( "Initializing mux %p\n", mux );
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mux->lastLockedFn = "(never locked)";
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mux->lastLockedLine = -1;
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#endif
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mux->owner = portMUX_FREE_VAL;
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mux->count = 0;
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}
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#include "portmux_impl.h"
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/*
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* For kernel use: Acquire a per-CPU mux. Spinlocks, so don't hold on to these muxes for too long.
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*/
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#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
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void vPortCPUAcquireMutex( portMUX_TYPE * mux,
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const char * fnName,
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int line )
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{
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unsigned int irqStatus = portSET_INTERRUPT_MASK_FROM_ISR();
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vPortCPUAcquireMutexIntsDisabled( mux, portMUX_NO_TIMEOUT, fnName, line );
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portCLEAR_INTERRUPT_MASK_FROM_ISR( irqStatus );
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}
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bool vPortCPUAcquireMutexTimeout( portMUX_TYPE * mux,
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int timeout_cycles,
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const char * fnName,
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int line )
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{
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unsigned int irqStatus = portSET_INTERRUPT_MASK_FROM_ISR();
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bool result = vPortCPUAcquireMutexIntsDisabled( mux, timeout_cycles, fnName, line );
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portCLEAR_INTERRUPT_MASK_FROM_ISR( irqStatus );
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return result;
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}
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#else /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */
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void vPortCPUAcquireMutex( portMUX_TYPE * mux )
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{
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unsigned int irqStatus = portSET_INTERRUPT_MASK_FROM_ISR();
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vPortCPUAcquireMutexIntsDisabled( mux, portMUX_NO_TIMEOUT );
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portCLEAR_INTERRUPT_MASK_FROM_ISR( irqStatus );
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}
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bool vPortCPUAcquireMutexTimeout( portMUX_TYPE * mux,
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int timeout_cycles )
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{
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unsigned int irqStatus = portSET_INTERRUPT_MASK_FROM_ISR();
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bool result = vPortCPUAcquireMutexIntsDisabled( mux, timeout_cycles );
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portCLEAR_INTERRUPT_MASK_FROM_ISR( irqStatus );
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return result;
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}
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#endif /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */
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/*
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* For kernel use: Release a per-CPU mux
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*
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* Mux must be already locked by this core
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*/
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#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
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void vPortCPUReleaseMutex( portMUX_TYPE * mux,
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const char * fnName,
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int line )
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{
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unsigned int irqStatus = portSET_INTERRUPT_MASK_FROM_ISR();
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vPortCPUReleaseMutexIntsDisabled( mux, fnName, line );
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portCLEAR_INTERRUPT_MASK_FROM_ISR( irqStatus );
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}
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#else
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void vPortCPUReleaseMutex( portMUX_TYPE * mux )
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{
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unsigned int irqStatus = portSET_INTERRUPT_MASK_FROM_ISR();
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vPortCPUReleaseMutexIntsDisabled( mux );
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portCLEAR_INTERRUPT_MASK_FROM_ISR( irqStatus );
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}
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#endif /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */
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#define STACK_WATCH_AREA_SIZE ( 32 )
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#define STACK_WATCH_POINT_NUMBER ( SOC_CPU_WATCHPOINTS_NUM - 1 )
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void vPortSetStackWatchpoint( void * pxStackStart )
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{
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/*Set watchpoint 1 to watch the last 32 bytes of the stack. */
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/*Unfortunately, the Xtensa watchpoints can't set a watchpoint on a random [base - base+n] region because */
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/*the size works by masking off the lowest address bits. For that reason, we futz a bit and watch the lowest 32 */
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/*bytes of the stack we can actually watch. In general, this can cause the watchpoint to be triggered at most */
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/*28 bytes early. The value 32 is chosen because it's larger than the stack canary, which in FreeRTOS is 20 bytes. */
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/*This way, we make sure we trigger before/when the stack canary is corrupted, not after. */
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int addr = ( int ) pxStackStart;
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addr = ( addr + 31 ) & ( ~31 );
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esp_cpu_set_watchpoint( STACK_WATCH_POINT_NUMBER, ( char * ) addr, 32, ESP_WATCHPOINT_STORE );
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}
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#if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) )
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|
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#if defined( CONFIG_SPIRAM_SUPPORT )
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|
|
|
/*
|
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* Compare & set (S32C1) does not work in external RAM. Instead, this routine uses a mux (in internal memory) to fake it.
|
|
*/
|
|
static portMUX_TYPE extram_mux = portMUX_INITIALIZER_UNLOCKED;
|
|
|
|
void uxPortCompareSetExtram( volatile uint32_t * addr,
|
|
uint32_t compare,
|
|
uint32_t * set )
|
|
{
|
|
uint32_t prev;
|
|
|
|
uint32_t oldlevel = portSET_INTERRUPT_MASK_FROM_ISR();
|
|
|
|
#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
|
|
vPortCPUAcquireMutexIntsDisabled( &extram_mux, portMUX_NO_TIMEOUT, __FUNCTION__, __LINE__ );
|
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#else
|
|
vPortCPUAcquireMutexIntsDisabled( &extram_mux, portMUX_NO_TIMEOUT );
|
|
#endif
|
|
prev = *addr;
|
|
|
|
if( prev == compare )
|
|
{
|
|
*addr = *set;
|
|
}
|
|
|
|
*set = prev;
|
|
#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
|
|
vPortCPUReleaseMutexIntsDisabled( &extram_mux, __FUNCTION__, __LINE__ );
|
|
#else
|
|
vPortCPUReleaseMutexIntsDisabled( &extram_mux );
|
|
#endif
|
|
|
|
portCLEAR_INTERRUPT_MASK_FROM_ISR( oldlevel );
|
|
}
|
|
#endif //defined(CONFIG_SPIRAM_SUPPORT)
|
|
|
|
#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */
|
|
|
|
|
|
uint32_t xPortGetTickRateHz( void )
|
|
{
|
|
return ( uint32_t ) configTICK_RATE_HZ;
|
|
}
|
|
|
|
/* For now, running FreeRTOS on one core and a bare metal on the other (or other OSes) */
|
|
/* is not supported. For now CONFIG_FREERTOS_UNICORE and CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE */
|
|
/* should mirror each other's values. */
|
|
/* */
|
|
/* And since this should be true, we can just check for CONFIG_FREERTOS_UNICORE. */
|
|
#if CONFIG_FREERTOS_UNICORE != CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
|
|
#error "FreeRTOS and system configuration mismatch regarding the use of multiple cores."
|
|
#endif
|
|
|
|
extern void esp_startup_start_app_common( void );
|
|
|
|
void esp_startup_start_app( void )
|
|
{
|
|
#if !CONFIG_ESP_INT_WDT
|
|
#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
|
|
assert( !soc_has_cache_lock_bug() && "ESP32 Rev 3 + Dual Core + PSRAM requires INT WDT enabled in project config!" );
|
|
#endif
|
|
#endif
|
|
|
|
esp_startup_start_app_common();
|
|
|
|
ESP_LOGI( "cpu_start", "Starting scheduler on PRO CPU." );
|
|
vTaskStartScheduler();
|
|
}
|