mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-11-04 11:09:01 +01:00
17dfd0f808
* Fix kexcept function * Create dummy pxCurrentTCBs for xcore.ai port * Additional commentary * Add a layer of indirection to cope with singlecore * Clarify use of _DoException
294 lines
9.2 KiB
C
294 lines
9.2 KiB
C
/* Copyright (c) 2019, XMOS Ltd, All rights reserved */
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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#include <string.h>
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#include <xs1.h>
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#include <xcore/hwtimer.h>
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#include <xcore/triggerable.h>
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static hwtimer_t xKernelTimer;
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uint32_t ulPortYieldRequired[ portMAX_CORE_COUNT ] = { pdFALSE };
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/* When this port was designed, it was assumed that pxCurrentTCBs would always
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exist and that it would always be an array containing pointers to the current
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TCBs for each core. In v11, this is not the case; if we are only running one
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core, the symbol is pxCurrentTCB instead. Therefore, this port adds a layer
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of indirection - we populate this pointer-to-pointer in the RTOS kernel entry
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function below. This makes this port agnostic to whether it is running on SMP
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or singlecore RTOS. */
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void ** xcorePvtTCBContainer;
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/*-----------------------------------------------------------*/
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void vIntercoreInterruptISR( void )
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{
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int xCoreID;
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/* debug_printf( "In KCALL: %u\n", ulData ); */
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xCoreID = rtos_core_id_get();
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ulPortYieldRequired[ xCoreID ] = pdTRUE;
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}
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/*-----------------------------------------------------------*/
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DEFINE_RTOS_INTERRUPT_CALLBACK( pxKernelTimerISR, pvData )
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{
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uint32_t ulLastTrigger;
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uint32_t ulNow;
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int xCoreID;
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UBaseType_t uxSavedInterruptStatus;
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xCoreID = 0;
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configASSERT( xCoreID == rtos_core_id_get() );
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/* Need the next interrupt to be scheduled relative to
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* the current trigger time, rather than the current
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* time. */
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ulLastTrigger = hwtimer_get_trigger_time( xKernelTimer );
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/* Check to see if the ISR is late. If it is, we don't
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* want to schedule the next interrupt to be in the past. */
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ulNow = hwtimer_get_time( xKernelTimer );
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if( ulNow - ulLastTrigger >= configCPU_CLOCK_HZ / configTICK_RATE_HZ )
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{
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ulLastTrigger = ulNow;
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}
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ulLastTrigger += configCPU_CLOCK_HZ / configTICK_RATE_HZ;
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hwtimer_change_trigger_time( xKernelTimer, ulLastTrigger );
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#if configUPDATE_RTOS_TIME_FROM_TICK_ISR == 1
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rtos_time_increment( RTOS_TICK_PERIOD( configTICK_RATE_HZ ) );
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#endif
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uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
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if( xTaskIncrementTick() != pdFALSE )
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{
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ulPortYieldRequired[ xCoreID ] = pdTRUE;
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}
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taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );
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}
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/*-----------------------------------------------------------*/
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void vPortYieldOtherCore( int xOtherCoreID )
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{
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int xCoreID;
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/*
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* This function must be called from within a critical section.
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*/
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xCoreID = rtos_core_id_get();
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/* debug_printf("%d->%d\n", xCoreID, xOtherCoreID); */
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/* debug_printf("Yield core %d from %d\n", xOtherCoreID, xCoreID ); */
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rtos_irq( xOtherCoreID, xCoreID );
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}
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/*-----------------------------------------------------------*/
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static int prvCoreInit( void )
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{
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int xCoreID;
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xCoreID = rtos_core_register();
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debug_printf( "Logical Core %d initializing as FreeRTOS Core %d\n", get_logical_core_id(), xCoreID );
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asm volatile (
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"ldap r11, kexcept\n\t"
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"set kep, r11\n\t"
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:
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:
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: "r11"
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);
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rtos_irq_enable( configNUMBER_OF_CORES );
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/*
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* All threads wait here until all have enabled IRQs
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*/
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while( rtos_irq_ready() == pdFALSE )
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{
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}
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if( xCoreID == 0 )
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{
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uint32_t ulNow;
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ulNow = hwtimer_get_time( xKernelTimer );
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/* debug_printf( "The time is now (%u)\n", ulNow ); */
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ulNow += configCPU_CLOCK_HZ / configTICK_RATE_HZ;
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triggerable_setup_interrupt_callback( xKernelTimer, NULL, RTOS_INTERRUPT_CALLBACK( pxKernelTimerISR ) );
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hwtimer_set_trigger_time( xKernelTimer, ulNow );
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triggerable_enable_trigger( xKernelTimer );
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}
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return xCoreID;
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}
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/*-----------------------------------------------------------*/
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DEFINE_RTOS_KERNEL_ENTRY( void, vPortStartSchedulerOnCore, void )
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{
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int xCoreID;
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xCoreID = prvCoreInit();
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#if ( configUSE_CORE_INIT_HOOK == 1 )
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{
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extern void vApplicationCoreInitHook( BaseType_t xCoreID );
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vApplicationCoreInitHook( xCoreID );
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}
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#endif
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/* Populate the TCBContainer depending on whether we're singlecore or SMP */
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#if ( configNUMBER_OF_CORES == 1 )
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{
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asm volatile (
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"ldaw %0, dp[pxCurrentTCB]\n\t"
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: "=r"(xcorePvtTCBContainer)
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: /* no inputs */
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: /* no clobbers */
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);
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}
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#else
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{
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asm volatile (
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"ldaw %0, dp[pxCurrentTCBs]\n\t"
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: "=r"(xcorePvtTCBContainer)
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: /* no inputs */
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: /* no clobbers */
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);
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}
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#endif
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debug_printf( "FreeRTOS Core %d initialized\n", xCoreID );
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/*
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* Restore the context of the first thread
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* to run and jump into it.
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*/
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asm volatile (
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"mov r6, %0\n\t" /* R6 must be the FreeRTOS core ID. In singlecore this is always 0. */
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"ldw r5, dp[xcorePvtTCBContainer]\n\t" /* R5 must be the TCB list which is indexed by R6 */
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"bu _freertos_restore_ctx\n\t"
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: /* no outputs */
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: "r" ( xCoreID )
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: "r5", "r6"
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);
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}
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/*-----------------------------------------------------------*/
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/*-----------------------------------------------------------*/
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/* Public functions required by all ports below: */
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/*-----------------------------------------------------------*/
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/*
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* See header file for description.
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*/
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StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
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TaskFunction_t pxCode,
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void * pvParameters )
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{
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/*debug_printf( "Top of stack was %p for task %p\n", pxTopOfStack, pxCode ); */
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/*
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* Grow the thread's stack by portTHREAD_CONTEXT_STACK_GROWTH
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* so we can push the context onto it.
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*/
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pxTopOfStack -= portTHREAD_CONTEXT_STACK_GROWTH;
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uint32_t dp;
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uint32_t cp;
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/*
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* We need to get the current CP and DP pointers.
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*/
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asm volatile (
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"ldaw r11, cp[0]\n\t" /* get CP into R11 */
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"mov %0, r11\n\t" /* get R11 (CP) into cp */
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"ldaw r11, dp[0]\n\t" /* get DP into R11 */
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"mov %1, r11\n\t" /* get R11 (DP) into dp */
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: "=r" ( cp ), "=r" ( dp ) /* output 0 is cp, output 1 is dp */
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: /* there are no inputs */
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: "r11" /* R11 gets clobbered */
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);
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/*
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* Push the thread context onto the stack.
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* Saved PC will point to the new thread's
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* entry pointer.
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* Interrupts will default to enabled.
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* KEDI is also set to enable dual issue mode
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* upon kernel entry.
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*/
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pxTopOfStack[ 1 ] = ( StackType_t ) pxCode; /* SP[1] := SPC */
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pxTopOfStack[ 2 ] = XS1_SR_IEBLE_MASK
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| XS1_SR_KEDI_MASK; /* SP[2] := SSR */
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pxTopOfStack[ 3 ] = 0x00000000; /* SP[3] := SED */
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pxTopOfStack[ 4 ] = 0x00000000; /* SP[4] := ET */
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pxTopOfStack[ 5 ] = dp; /* SP[5] := DP */
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pxTopOfStack[ 6 ] = cp; /* SP[6] := CP */
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pxTopOfStack[ 7 ] = 0x00000000; /* SP[7] := LR */
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pxTopOfStack[ 8 ] = ( StackType_t ) pvParameters; /* SP[8] := R0 */
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pxTopOfStack[ 9 ] = 0x01010101; /* SP[9] := R1 */
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pxTopOfStack[ 10 ] = 0x02020202; /* SP[10] := R2 */
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pxTopOfStack[ 11 ] = 0x03030303; /* SP[11] := R3 */
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pxTopOfStack[ 12 ] = 0x04040404; /* SP[12] := R4 */
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pxTopOfStack[ 13 ] = 0x05050505; /* SP[13] := R5 */
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pxTopOfStack[ 14 ] = 0x06060606; /* SP[14] := R6 */
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pxTopOfStack[ 15 ] = 0x07070707; /* SP[15] := R7 */
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pxTopOfStack[ 16 ] = 0x08080808; /* SP[16] := R8 */
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pxTopOfStack[ 17 ] = 0x09090909; /* SP[17] := R9 */
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pxTopOfStack[ 18 ] = 0x10101010; /* SP[18] := R10 */
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pxTopOfStack[ 19 ] = 0x11111111; /* SP[19] := R11 */
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pxTopOfStack[ 20 ] = 0x00000000; /* SP[20] := vH and vSR */
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memset( &pxTopOfStack[ 21 ], 0, 32 ); /* SP[21 - 28] := vR */
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memset( &pxTopOfStack[ 29 ], 1, 32 ); /* SP[29 - 36] := vD */
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memset( &pxTopOfStack[ 37 ], 2, 32 ); /* SP[37 - 44] := vC */
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/*debug_printf( "Top of stack is now %p for task %p\n", pxTopOfStack, pxCode ); */
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/*
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* Returns the new top of the stack
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*/
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return pxTopOfStack;
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}
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/*-----------------------------------------------------------*/
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void vPortStartSMPScheduler( void );
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/*
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* See header file for description.
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*/
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BaseType_t xPortStartScheduler( void )
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{
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if( ( configNUMBER_OF_CORES > portMAX_CORE_COUNT ) || ( configNUMBER_OF_CORES <= 0 ) )
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{
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return pdFAIL;
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}
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rtos_locks_initialize();
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xKernelTimer = hwtimer_alloc();
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vPortStartSMPScheduler();
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return pdPASS;
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}
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/*-----------------------------------------------------------*/
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void vPortEndScheduler( void )
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{
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/* Do not implement. */
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}
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/*-----------------------------------------------------------*/
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