mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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de276eb023
* Fix spelling --------- Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
557 lines
22 KiB
C
557 lines
22 KiB
C
/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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/* Standard includes. */
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#include <stdlib.h>
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
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#error "configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
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#endif
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#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
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#error "configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
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#endif
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#ifndef configUNIQUE_INTERRUPT_PRIORITIES
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#error "configUNIQUE_INTERRUPT_PRIORITIES must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
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#endif
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#ifndef configSETUP_TICK_INTERRUPT
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#error "configSETUP_TICK_INTERRUPT() must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
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#endif /* configSETUP_TICK_INTERRUPT */
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#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
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#error "configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
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#endif
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#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
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#error "configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0"
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#endif
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#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
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#error "configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority"
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#endif
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#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
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/* Check the configuration. */
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#if ( configMAX_PRIORITIES > 32 )
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#error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice."
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#endif
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#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
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/* In case security extensions are implemented. */
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#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
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#error "configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )"
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#endif
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/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
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* portmacro.h. */
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#ifndef configCLEAR_TICK_INTERRUPT
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#define configCLEAR_TICK_INTERRUPT()
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#endif
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/* A critical section is exited when the critical section nesting count reaches
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* this value. */
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#define portNO_CRITICAL_NESTING ( ( size_t ) 0 )
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/* In all GICs 255 can be written to the priority mask register to unmask all
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* (but the lowest) interrupt priority. */
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#define portUNMASK_VALUE ( 0xFFUL )
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/* Tasks are not created with a floating point context, but can be given a
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* floating point context after they have been created. A variable is stored as
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* part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
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* does not have an FPU context, or any other value if the task does have an FPU
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* context. */
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#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
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/* Constants required to setup the initial task context. */
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#define portSP_ELx ( ( StackType_t ) 0x01 )
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#define portSP_EL0 ( ( StackType_t ) 0x00 )
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#if defined( GUEST )
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#define portEL1 ( ( StackType_t ) 0x04 )
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#define portINITIAL_PSTATE ( portEL1 | portSP_EL0 )
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#else
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#define portEL3 ( ( StackType_t ) 0x0c )
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/* At the time of writing, the BSP only supports EL3. */
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#define portINITIAL_PSTATE ( portEL3 | portSP_EL0 )
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#endif
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/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
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* point is zero. */
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#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
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/* Masks all bits in the APSR other than the mode bits. */
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#define portAPSR_MODE_BITS_MASK ( 0x0C )
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/* The I bit in the DAIF bits. */
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#define portDAIF_I ( 0x80 )
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/* Macro to unmask all interrupt priorities. */
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#define portCLEAR_INTERRUPT_MASK() \
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{ \
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portDISABLE_INTERRUPTS(); \
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portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
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__asm volatile ( "DSB SY \n" \
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"ISB SY \n" ); \
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portENABLE_INTERRUPTS(); \
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}
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/* Hardware specifics used when sanity checking the configuration. */
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#define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL
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#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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#define portBIT_0_SET ( ( uint8_t ) 0x01 )
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/* The space on the stack required to hold the FPU registers.
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* There are 32 128-bit registers.*/
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#define portFPU_REGISTER_WORDS ( 32 * 2 )
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/*-----------------------------------------------------------*/
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/*
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* Starts the first task executing. This function is necessarily written in
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* assembly code so is implemented in portASM.s.
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*/
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extern void vPortRestoreTaskContext( void );
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/*-----------------------------------------------------------*/
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/* A variable is used to keep track of the critical section nesting. This
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* variable has to be stored as part of the task context and must be initialised to
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* a non zero value to ensure interrupts don't inadvertently become unmasked before
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* the scheduler starts. As it is stored as part of the task context it will
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* automatically be set to 0 when the first task is started. */
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volatile uint64_t ullCriticalNesting = 9999ULL;
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/* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero
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* then floating point context must be saved and restored for the task. */
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uint64_t ullPortTaskHasFPUContext = pdFALSE;
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/* Set to 1 to pend a context switch from an ISR. */
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uint64_t ullPortYieldRequired = pdFALSE;
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/* Counts the interrupt nesting depth. A context switch is only performed if
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* if the nesting depth is 0. */
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uint64_t ullPortInterruptNesting = 0;
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/* Used in the ASM code. */
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__attribute__( ( used ) ) const uint64_t ullICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
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__attribute__( ( used ) ) const uint64_t ullICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
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__attribute__( ( used ) ) const uint64_t ullICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
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__attribute__( ( used ) ) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
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/*-----------------------------------------------------------*/
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/*
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* See header file for description.
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*/
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StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
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TaskFunction_t pxCode,
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void * pvParameters )
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{
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/* Setup the initial stack of the task. The stack is set exactly as
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* expected by the portRESTORE_CONTEXT() macro. */
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/* First all the general purpose registers. */
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pxTopOfStack--;
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*pxTopOfStack = 0x0101010101010101ULL; /* R1 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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pxTopOfStack--;
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*pxTopOfStack = 0x0303030303030303ULL; /* R3 */
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pxTopOfStack--;
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*pxTopOfStack = 0x0202020202020202ULL; /* R2 */
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pxTopOfStack--;
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*pxTopOfStack = 0x0505050505050505ULL; /* R5 */
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pxTopOfStack--;
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*pxTopOfStack = 0x0404040404040404ULL; /* R4 */
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pxTopOfStack--;
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*pxTopOfStack = 0x0707070707070707ULL; /* R7 */
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pxTopOfStack--;
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*pxTopOfStack = 0x0606060606060606ULL; /* R6 */
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pxTopOfStack--;
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*pxTopOfStack = 0x0909090909090909ULL; /* R9 */
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pxTopOfStack--;
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*pxTopOfStack = 0x0808080808080808ULL; /* R8 */
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pxTopOfStack--;
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*pxTopOfStack = 0x1111111111111111ULL; /* R11 */
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pxTopOfStack--;
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*pxTopOfStack = 0x1010101010101010ULL; /* R10 */
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pxTopOfStack--;
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*pxTopOfStack = 0x1313131313131313ULL; /* R13 */
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pxTopOfStack--;
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*pxTopOfStack = 0x1212121212121212ULL; /* R12 */
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pxTopOfStack--;
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*pxTopOfStack = 0x1515151515151515ULL; /* R15 */
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pxTopOfStack--;
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*pxTopOfStack = 0x1414141414141414ULL; /* R14 */
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pxTopOfStack--;
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*pxTopOfStack = 0x1717171717171717ULL; /* R17 */
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pxTopOfStack--;
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*pxTopOfStack = 0x1616161616161616ULL; /* R16 */
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pxTopOfStack--;
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*pxTopOfStack = 0x1919191919191919ULL; /* R19 */
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pxTopOfStack--;
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*pxTopOfStack = 0x1818181818181818ULL; /* R18 */
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pxTopOfStack--;
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*pxTopOfStack = 0x2121212121212121ULL; /* R21 */
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pxTopOfStack--;
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*pxTopOfStack = 0x2020202020202020ULL; /* R20 */
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pxTopOfStack--;
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*pxTopOfStack = 0x2323232323232323ULL; /* R23 */
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pxTopOfStack--;
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*pxTopOfStack = 0x2222222222222222ULL; /* R22 */
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pxTopOfStack--;
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*pxTopOfStack = 0x2525252525252525ULL; /* R25 */
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pxTopOfStack--;
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*pxTopOfStack = 0x2424242424242424ULL; /* R24 */
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pxTopOfStack--;
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*pxTopOfStack = 0x2727272727272727ULL; /* R27 */
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pxTopOfStack--;
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*pxTopOfStack = 0x2626262626262626ULL; /* R26 */
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pxTopOfStack--;
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*pxTopOfStack = 0x2929292929292929ULL; /* R29 */
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pxTopOfStack--;
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*pxTopOfStack = 0x2828282828282828ULL; /* R28 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x00; /* XZR - has no effect, used so there are an even number of registers. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x00; /* R30 - procedure call link register. */
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pxTopOfStack--;
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*pxTopOfStack = portINITIAL_PSTATE;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) pxCode; /* Exception return address. */
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#if ( configUSE_TASK_FPU_SUPPORT == 1 )
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{
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/* The task will start with a critical nesting count of 0 as interrupts are
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* enabled. */
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pxTopOfStack--;
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*pxTopOfStack = portNO_CRITICAL_NESTING;
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/* The task will start without a floating point context. A task that
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* uses the floating point hardware must call vPortTaskUsesFPU() before
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* executing any floating point instructions. */
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pxTopOfStack--;
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*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
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}
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#elif ( configUSE_TASK_FPU_SUPPORT == 2 )
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{
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/* The task will start with a floating point context. Leave enough
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* space for the registers - and ensure they are initialised to 0. */
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pxTopOfStack -= portFPU_REGISTER_WORDS;
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memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) );
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/* The task will start with a critical nesting count of 0 as interrupts are
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* enabled. */
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pxTopOfStack--;
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*pxTopOfStack = portNO_CRITICAL_NESTING;
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pxTopOfStack--;
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*pxTopOfStack = pdTRUE;
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ullPortTaskHasFPUContext = pdTRUE;
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}
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#else /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */
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{
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#error "Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined."
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}
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#endif /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */
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return pxTopOfStack;
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}
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/*-----------------------------------------------------------*/
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BaseType_t xPortStartScheduler( void )
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{
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uint32_t ulAPSR;
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#if ( configASSERT_DEFINED == 1 )
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{
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volatile uint8_t ucOriginalPriority;
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volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
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volatile uint8_t ucMaxPriorityValue;
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/* Determine how many priority bits are implemented in the GIC.
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*
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* Save the interrupt priority value that is about to be clobbered. */
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ucOriginalPriority = *pucFirstUserPriorityRegister;
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/* Determine the number of priority bits available. First write to
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* all possible bits. */
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*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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/* Read the value back to see how many bits stuck. */
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ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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/* Shift to the least significant bits. */
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while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
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{
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ucMaxPriorityValue >>= ( uint8_t ) 0x01;
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}
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/* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
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* value. */
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configASSERT( ucMaxPriorityValue >= portLOWEST_INTERRUPT_PRIORITY );
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/* Restore the clobbered interrupt priority register to its original
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* value. */
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*pucFirstUserPriorityRegister = ucOriginalPriority;
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}
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#endif /* configASSERT_DEFINED */
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/* At the time of writing, the BSP only supports EL3. */
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__asm volatile ( "MRS %0, CurrentEL" : "=r" ( ulAPSR ) );
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ulAPSR &= portAPSR_MODE_BITS_MASK;
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#if defined( GUEST )
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#warning "Building for execution as a guest under XEN. THIS IS NOT A FULLY TESTED PATH."
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configASSERT( ulAPSR == portEL1 );
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if( ulAPSR == portEL1 )
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#else
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configASSERT( ulAPSR == portEL3 );
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if( ulAPSR == portEL3 )
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#endif
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{
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/* Only continue if the binary point value is set to its lowest possible
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* setting. See the comments in vPortValidateInterruptPriority() below for
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* more information. */
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configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
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if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
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{
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/* Interrupts are turned off in the CPU itself to ensure a tick does
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* not execute while the scheduler is being started. Interrupts are
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* automatically turned back on in the CPU when the first task starts
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* executing. */
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portDISABLE_INTERRUPTS();
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/* Start the timer that generates the tick ISR. */
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configSETUP_TICK_INTERRUPT();
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/* Start the first task executing. */
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vPortRestoreTaskContext();
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}
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}
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return 0;
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}
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/*-----------------------------------------------------------*/
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void vPortEndScheduler( void )
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{
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/* Not implemented in ports where there is nothing to return to.
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* Artificially force an assert. */
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configASSERT( ullCriticalNesting == 1000ULL );
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}
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/*-----------------------------------------------------------*/
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void vPortEnterCritical( void )
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{
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/* Mask interrupts up to the max syscall interrupt priority. */
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uxPortSetInterruptMask();
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/* Now interrupts are disabled ullCriticalNesting can be accessed
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* directly. Increment ullCriticalNesting to keep a count of how many times
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* portENTER_CRITICAL() has been called. */
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ullCriticalNesting++;
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/* This is not the interrupt safe version of the enter critical function so
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* assert() if it is being called from an interrupt context. Only API
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* functions that end in "FromISR" can be used in an interrupt. Only assert if
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* the critical nesting count is 1 to protect against recursive calls if the
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* assert function also uses a critical section. */
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if( ullCriticalNesting == 1ULL )
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{
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configASSERT( ullPortInterruptNesting == 0 );
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}
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}
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/*-----------------------------------------------------------*/
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void vPortExitCritical( void )
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{
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if( ullCriticalNesting > portNO_CRITICAL_NESTING )
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{
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/* Decrement the nesting count as the critical section is being
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* exited. */
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ullCriticalNesting--;
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/* If the nesting level has reached zero then all interrupt
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* priorities must be re-enabled. */
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if( ullCriticalNesting == portNO_CRITICAL_NESTING )
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{
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/* Critical nesting has reached zero so all interrupt priorities
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* should be unmasked. */
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portCLEAR_INTERRUPT_MASK();
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}
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}
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}
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/*-----------------------------------------------------------*/
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void FreeRTOS_Tick_Handler( void )
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{
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/* Must be the lowest possible priority. */
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#if !defined( QEMU )
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{
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configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER == ( uint32_t ) ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
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}
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#endif
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/* Interrupts should not be enabled before this point. */
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#if ( configASSERT_DEFINED == 1 )
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{
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uint32_t ulMaskBits;
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__asm volatile ( "mrs %0, daif" : "=r" ( ulMaskBits )::"memory" );
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configASSERT( ( ulMaskBits & portDAIF_I ) != 0 );
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}
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#endif /* configASSERT_DEFINED */
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/* Set interrupt mask before altering scheduler structures. The tick
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* handler runs at the lowest priority, so interrupts cannot already be masked,
|
|
* so there is no need to save and restore the current mask value. It is
|
|
* necessary to turn off interrupts in the CPU itself while the ICCPMR is being
|
|
* updated. */
|
|
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
|
|
__asm volatile ( "dsb sy \n"
|
|
"isb sy \n" ::: "memory" );
|
|
|
|
/* Ok to enable interrupts after the interrupt source has been cleared. */
|
|
configCLEAR_TICK_INTERRUPT();
|
|
portENABLE_INTERRUPTS();
|
|
|
|
/* Increment the RTOS tick. */
|
|
if( xTaskIncrementTick() != pdFALSE )
|
|
{
|
|
ullPortYieldRequired = pdTRUE;
|
|
}
|
|
|
|
/* Ensure all interrupt priorities are active again. */
|
|
portCLEAR_INTERRUPT_MASK();
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configUSE_TASK_FPU_SUPPORT != 2 )
|
|
|
|
void vPortTaskUsesFPU( void )
|
|
{
|
|
/* A task is registering the fact that it needs an FPU context. Set the
|
|
* FPU flag (which is saved as part of the task context). */
|
|
ullPortTaskHasFPUContext = pdTRUE;
|
|
|
|
/* Consider initialising the FPSR here - but probably not necessary in
|
|
* AArch64. */
|
|
}
|
|
|
|
#endif /* configUSE_TASK_FPU_SUPPORT */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortClearInterruptMask( UBaseType_t uxNewMaskValue )
|
|
{
|
|
if( uxNewMaskValue == pdFALSE )
|
|
{
|
|
portCLEAR_INTERRUPT_MASK();
|
|
}
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
UBaseType_t uxPortSetInterruptMask( void )
|
|
{
|
|
uint32_t ulReturn;
|
|
|
|
/* Interrupt in the CPU must be turned off while the ICCPMR is being
|
|
* updated. */
|
|
portDISABLE_INTERRUPTS();
|
|
|
|
if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
|
|
{
|
|
/* Interrupts were already masked. */
|
|
ulReturn = pdTRUE;
|
|
}
|
|
else
|
|
{
|
|
ulReturn = pdFALSE;
|
|
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
|
|
__asm volatile ( "dsb sy \n"
|
|
"isb sy \n" ::: "memory" );
|
|
}
|
|
|
|
portENABLE_INTERRUPTS();
|
|
|
|
return ulReturn;
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configASSERT_DEFINED == 1 )
|
|
|
|
void vPortValidateInterruptPriority( void )
|
|
{
|
|
/* The following assertion will fail if a service routine (ISR) for
|
|
* an interrupt that has been assigned a priority above
|
|
* configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
|
|
* function. ISR safe FreeRTOS API functions must *only* be called
|
|
* from interrupts that have been assigned a priority at or below
|
|
* configMAX_SYSCALL_INTERRUPT_PRIORITY.
|
|
*
|
|
* Numerically low interrupt priority numbers represent logically high
|
|
* interrupt priorities, therefore the priority of the interrupt must
|
|
* be set to a value equal to or numerically *higher* than
|
|
* configMAX_SYSCALL_INTERRUPT_PRIORITY.
|
|
*
|
|
* FreeRTOS maintains separate thread and ISR API functions to ensure
|
|
* interrupt entry is as fast and simple as possible. */
|
|
configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
|
|
|
|
/* Priority grouping: The interrupt controller (GIC) allows the bits
|
|
* that define each interrupt's priority to be split between bits that
|
|
* define the interrupt's pre-emption priority bits and bits that define
|
|
* the interrupt's sub-priority. For simplicity all bits must be defined
|
|
* to be pre-emption priority bits. The following assertion will fail if
|
|
* this is not the case (if some bits represent a sub-priority).
|
|
*
|
|
* The priority grouping is configured by the GIC's binary point register
|
|
* (ICCBPR). Writing 0 to ICCBPR will ensure it is set to its lowest
|
|
* possible value (which may be above 0). */
|
|
configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
|
|
}
|
|
|
|
#endif /* configASSERT_DEFINED */
|
|
/*-----------------------------------------------------------*/
|