mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-11-04 11:09:01 +01:00
72bb476bf3
The application writer needs to name their IRQ handler as: 1. vApplicationIRQHandler if the IRQ handler does not use FPU registers. 2. vApplicationFPUSafeIRQHandler is the IRQ handler uses FPU registers. When the application uses vApplicationFPUSafeIRQHandler, a default implementation of vApplicationIRQHandler is used which stores FPU registers and then calls vApplicationFPUSafeIRQHandler. Note that recent versions of GCC may use FP/SIMD registers to optimize 16-bytes copy and especially when using va_start()/va_arg() functions (e.g printing some thing in IRQ handlers may trigger usage of FPU registers) This implementation is heavily inspired by both the ARM_CA9 port and the ARM_CRx_No_GIC port done in [1] [1] https://github.com/FreeRTOS/FreeRTOS-Kernel/pull/1113 Signed-off-by: Marouen Ghodhbane <marouen.ghodhbane@nxp.com>
504 lines
16 KiB
ArmAsm
504 lines
16 KiB
ArmAsm
/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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.text
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/* Variables and functions. */
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.extern ullMaxAPIPriorityMask
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.extern pxCurrentTCB
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.extern vTaskSwitchContext
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.extern vApplicationIRQHandler
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.extern ullPortInterruptNesting
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.extern ullPortTaskHasFPUContext
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.extern ullCriticalNesting
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.extern ullPortYieldRequired
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.extern _freertos_vector_table
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.global FreeRTOS_IRQ_Handler
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.global FreeRTOS_SWI_Handler
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.global vPortRestoreTaskContext
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.macro portSAVE_CONTEXT
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/* Switch to use the EL0 stack pointer. */
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MSR SPSEL, #0
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/* Save the entire context. */
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STP X0, X1, [SP, #-0x10]!
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STP X2, X3, [SP, #-0x10]!
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STP X4, X5, [SP, #-0x10]!
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STP X6, X7, [SP, #-0x10]!
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STP X8, X9, [SP, #-0x10]!
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STP X10, X11, [SP, #-0x10]!
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STP X12, X13, [SP, #-0x10]!
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STP X14, X15, [SP, #-0x10]!
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STP X16, X17, [SP, #-0x10]!
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STP X18, X19, [SP, #-0x10]!
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STP X20, X21, [SP, #-0x10]!
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STP X22, X23, [SP, #-0x10]!
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STP X24, X25, [SP, #-0x10]!
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STP X26, X27, [SP, #-0x10]!
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STP X28, X29, [SP, #-0x10]!
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STP X30, XZR, [SP, #-0x10]!
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/* Save the SPSR. */
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#if defined( GUEST )
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MRS X3, SPSR_EL1
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MRS X2, ELR_EL1
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#else
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MRS X3, SPSR_EL3
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/* Save the ELR. */
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MRS X2, ELR_EL3
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#endif
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STP X2, X3, [SP, #-0x10]!
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/* Save the critical section nesting depth. */
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LDR X0, ullCriticalNestingConst
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LDR X3, [X0]
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/* Save the FPU context indicator. */
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LDR X0, ullPortTaskHasFPUContextConst
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LDR X2, [X0]
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/* Save the FPU context, if any (32 128-bit plus two 64-bit status registers). */
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CMP X2, #0
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B.EQ 1f
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STP Q0, Q1, [SP,#-0x20]!
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STP Q2, Q3, [SP,#-0x20]!
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STP Q4, Q5, [SP,#-0x20]!
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STP Q6, Q7, [SP,#-0x20]!
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STP Q8, Q9, [SP,#-0x20]!
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STP Q10, Q11, [SP,#-0x20]!
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STP Q12, Q13, [SP,#-0x20]!
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STP Q14, Q15, [SP,#-0x20]!
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STP Q16, Q17, [SP,#-0x20]!
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STP Q18, Q19, [SP,#-0x20]!
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STP Q20, Q21, [SP,#-0x20]!
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STP Q22, Q23, [SP,#-0x20]!
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STP Q24, Q25, [SP,#-0x20]!
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STP Q26, Q27, [SP,#-0x20]!
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STP Q28, Q29, [SP,#-0x20]!
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STP Q30, Q31, [SP,#-0x20]!
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/* Even though upper 32 bits of FPSR and FPCR are reserved, save and restore the whole 64 bits to keep 16-byte SP alignement. */
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MRS X9, FPSR
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MRS X10, FPCR
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STP X9, X10, [SP, #-0x10]!
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1:
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/* Store the critical nesting count and FPU context indicator. */
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STP X2, X3, [SP, #-0x10]!
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LDR X0, pxCurrentTCBConst
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LDR X1, [X0]
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MOV X0, SP /* Move SP into X0 for saving. */
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STR X0, [X1]
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/* Switch to use the ELx stack pointer. */
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MSR SPSEL, #1
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.endm
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; /**********************************************************************/
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.macro portRESTORE_CONTEXT
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/* Switch to use the EL0 stack pointer. */
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MSR SPSEL, #0
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/* Set the SP to point to the stack of the task being restored. */
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LDR X0, pxCurrentTCBConst
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LDR X1, [X0]
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LDR X0, [X1]
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MOV SP, X0
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LDP X2, X3, [SP], #0x10 /* Critical nesting and FPU context. */
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/* Set the PMR register to be correct for the current critical nesting
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depth. */
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LDR X0, ullCriticalNestingConst /* X0 holds the address of ullCriticalNesting. */
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MOV X1, #255 /* X1 holds the unmask value. */
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CMP X3, #0
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B.EQ 1f
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LDR X6, ullMaxAPIPriorityMaskConst
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LDR X1, [X6] /* X1 holds the mask value. */
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1:
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MSR s3_0_c4_c6_0, X1 /* Write the mask value to ICCPMR. s3_0_c4_c6_0 is ICC_PMR_EL1. */
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DSB SY /* _RB_Barriers probably not required here. */
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ISB SY
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STR X3, [X0] /* Restore the task's critical nesting count. */
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/* Restore the FPU context indicator. */
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LDR X0, ullPortTaskHasFPUContextConst
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STR X2, [X0]
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/* Restore the FPU context, if any. */
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CMP X2, #0
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B.EQ 1f
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LDP X9, X10, [SP], #0x10
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LDP Q30, Q31, [SP], #0x20
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LDP Q28, Q29, [SP], #0x20
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LDP Q26, Q27, [SP], #0x20
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LDP Q24, Q25, [SP], #0x20
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LDP Q22, Q23, [SP], #0x20
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LDP Q20, Q21, [SP], #0x20
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LDP Q18, Q19, [SP], #0x20
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LDP Q16, Q17, [SP], #0x20
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LDP Q14, Q15, [SP], #0x20
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LDP Q12, Q13, [SP], #0x20
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LDP Q10, Q11, [SP], #0x20
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LDP Q8, Q9, [SP], #0x20
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LDP Q6, Q7, [SP], #0x20
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LDP Q4, Q5, [SP], #0x20
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LDP Q2, Q3, [SP], #0x20
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LDP Q0, Q1, [SP], #0x20
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MSR FPSR, X9
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MSR FPCR, X10
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1:
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LDP X2, X3, [SP], #0x10 /* SPSR and ELR. */
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#if defined( GUEST )
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/* Restore the SPSR. */
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MSR SPSR_EL1, X3
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/* Restore the ELR. */
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MSR ELR_EL1, X2
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#else
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/* Restore the SPSR. */
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MSR SPSR_EL3, X3 /*_RB_ Assumes started in EL3. */
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/* Restore the ELR. */
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MSR ELR_EL3, X2
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#endif
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LDP X30, XZR, [SP], #0x10
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LDP X28, X29, [SP], #0x10
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LDP X26, X27, [SP], #0x10
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LDP X24, X25, [SP], #0x10
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LDP X22, X23, [SP], #0x10
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LDP X20, X21, [SP], #0x10
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LDP X18, X19, [SP], #0x10
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LDP X16, X17, [SP], #0x10
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LDP X14, X15, [SP], #0x10
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LDP X12, X13, [SP], #0x10
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LDP X10, X11, [SP], #0x10
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LDP X8, X9, [SP], #0x10
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LDP X6, X7, [SP], #0x10
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LDP X4, X5, [SP], #0x10
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LDP X2, X3, [SP], #0x10
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LDP X0, X1, [SP], #0x10
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/* Switch to use the ELx stack pointer. _RB_ Might not be required. */
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MSR SPSEL, #1
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ERET
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.endm
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/******************************************************************************
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* FreeRTOS_SWI_Handler handler is used to perform a context switch.
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*****************************************************************************/
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.align 8
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.type FreeRTOS_SWI_Handler, %function
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FreeRTOS_SWI_Handler:
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/* Save the context of the current task and select a new task to run. */
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portSAVE_CONTEXT
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#if defined( GUEST )
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MRS X0, ESR_EL1
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#else
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MRS X0, ESR_EL3
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#endif
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LSR X1, X0, #26
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#if defined( GUEST )
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CMP X1, #0x15 /* 0x15 = SVC instruction. */
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#else
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CMP X1, #0x17 /* 0x17 = SMC instruction. */
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#endif
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B.NE FreeRTOS_Abort
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BL vTaskSwitchContext
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portRESTORE_CONTEXT
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FreeRTOS_Abort:
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/* Full ESR is in X0, exception class code is in X1. */
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B .
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/******************************************************************************
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* vPortRestoreTaskContext is used to start the scheduler.
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*****************************************************************************/
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.align 8
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.type vPortRestoreTaskContext, %function
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vPortRestoreTaskContext:
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.set freertos_vector_base, _freertos_vector_table
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/* Install the FreeRTOS interrupt handlers. */
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LDR X1, =freertos_vector_base
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#if defined( GUEST )
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MSR VBAR_EL1, X1
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#else
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MSR VBAR_EL3, X1
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#endif
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DSB SY
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ISB SY
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/* Start the first task. */
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portRESTORE_CONTEXT
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/******************************************************************************
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* FreeRTOS_IRQ_Handler handles IRQ entry and exit.
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* This handler is supposed to be used only for IRQs and never for FIQs. Per ARM
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* GIC documentation [1], Group 0 interrupts are always signaled as FIQs. Since
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* this handler is only for IRQs, We can safely assume Group 1 while accessing
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* Interrupt Acknowledge and End Of Interrupt registers and therefore, use
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* ICC_IAR1_EL1 and ICC_EOIR1_EL1.
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*
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* [1] https://developer.arm.com/documentation/198123/0300/Arm-CoreLink-GIC-fundamentals
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*****************************************************************************/
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.align 8
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.type FreeRTOS_IRQ_Handler, %function
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FreeRTOS_IRQ_Handler:
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/* Save volatile registers. */
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STP X0, X1, [SP, #-0x10]!
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STP X2, X3, [SP, #-0x10]!
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STP X4, X5, [SP, #-0x10]!
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STP X6, X7, [SP, #-0x10]!
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STP X8, X9, [SP, #-0x10]!
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STP X10, X11, [SP, #-0x10]!
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STP X12, X13, [SP, #-0x10]!
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STP X14, X15, [SP, #-0x10]!
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STP X16, X17, [SP, #-0x10]!
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STP X18, X19, [SP, #-0x10]!
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STP X29, X30, [SP, #-0x10]!
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/* Save the SPSR and ELR. */
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#if defined( GUEST )
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MRS X3, SPSR_EL1
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MRS X2, ELR_EL1
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#else
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MRS X3, SPSR_EL3
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MRS X2, ELR_EL3
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#endif
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STP X2, X3, [SP, #-0x10]!
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/* Increment the interrupt nesting counter. */
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LDR X5, ullPortInterruptNestingConst
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LDR X1, [X5] /* Old nesting count in X1. */
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ADD X6, X1, #1
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STR X6, [X5] /* Address of nesting count variable in X5. */
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/* Maintain the interrupt nesting information across the function call. */
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STP X1, X5, [SP, #-0x10]!
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/* Read interrupt ID from the interrupt acknowledge register and store it
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in X0 for future parameter and interrupt clearing use. */
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MRS X0, S3_0_C12_C12_0 /* S3_0_C12_C12_0 is ICC_IAR1_EL1. */
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/* Maintain the interrupt ID value across the function call. */
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STP X0, X1, [SP, #-0x10]!
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/* Call the C handler. */
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BL vApplicationIRQHandler
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/* Disable interrupts. */
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MSR DAIFSET, #2
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DSB SY
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ISB SY
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/* Restore the interrupt ID value. */
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LDP X0, X1, [SP], #0x10
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/* End IRQ processing by writing interrupt ID value to the EOI register. */
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MSR S3_0_C12_C12_1, X0 /* S3_0_C12_C12_1 is ICC_EOIR1_EL1. */
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/* Restore the critical nesting count. */
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LDP X1, X5, [SP], #0x10
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STR X1, [X5]
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/* Has interrupt nesting unwound? */
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CMP X1, #0
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B.NE Exit_IRQ_No_Context_Switch
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/* Is a context switch required? */
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LDR X0, ullPortYieldRequiredConst
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LDR X1, [X0]
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CMP X1, #0
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B.EQ Exit_IRQ_No_Context_Switch
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/* Reset ullPortYieldRequired to 0. */
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MOV X2, #0
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STR X2, [X0]
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/* Restore volatile registers. */
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LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */
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#if defined( GUEST )
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MSR SPSR_EL1, X5
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MSR ELR_EL1, X4
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#else
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MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
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MSR ELR_EL3, X4
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#endif
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DSB SY
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ISB SY
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LDP X29, X30, [SP], #0x10
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LDP X18, X19, [SP], #0x10
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LDP X16, X17, [SP], #0x10
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LDP X14, X15, [SP], #0x10
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LDP X12, X13, [SP], #0x10
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LDP X10, X11, [SP], #0x10
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LDP X8, X9, [SP], #0x10
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LDP X6, X7, [SP], #0x10
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LDP X4, X5, [SP], #0x10
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LDP X2, X3, [SP], #0x10
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LDP X0, X1, [SP], #0x10
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/* Save the context of the current task and select a new task to run. */
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portSAVE_CONTEXT
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BL vTaskSwitchContext
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portRESTORE_CONTEXT
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Exit_IRQ_No_Context_Switch:
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/* Restore volatile registers. */
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LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */
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#if defined( GUEST )
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MSR SPSR_EL1, X5
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MSR ELR_EL1, X4
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#else
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MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
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MSR ELR_EL3, X4
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#endif
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DSB SY
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ISB SY
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LDP X29, X30, [SP], #0x10
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LDP X18, X19, [SP], #0x10
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LDP X16, X17, [SP], #0x10
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LDP X14, X15, [SP], #0x10
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LDP X12, X13, [SP], #0x10
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LDP X10, X11, [SP], #0x10
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LDP X8, X9, [SP], #0x10
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LDP X6, X7, [SP], #0x10
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LDP X4, X5, [SP], #0x10
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LDP X2, X3, [SP], #0x10
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LDP X0, X1, [SP], #0x10
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ERET
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/******************************************************************************
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* If the application provides an implementation of vApplicationIRQHandler(),
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* then it will get called directly without saving the FPU registers on
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* interrupt entry, and this weak implementation of
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* vApplicationIRQHandler() will not get called.
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*
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* If the application provides its own implementation of
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* vApplicationFPUSafeIRQHandler() then this implementation of
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* vApplicationIRQHandler() will be called, save the FPU registers, and then
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* call vApplicationFPUSafeIRQHandler().
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*
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* Therefore, if the application writer wants FPU registers to be saved on
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* interrupt entry their IRQ handler must be called
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* vApplicationFPUSafeIRQHandler(), and if the application writer does not want
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* FPU registers to be saved on interrupt entry their IRQ handler must be
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* called vApplicationIRQHandler().
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*****************************************************************************/
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.align 8
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.weak vApplicationIRQHandler
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.type vApplicationIRQHandler, %function
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vApplicationIRQHandler:
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/* Save LR and FP on the stack */
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STP X29, X30, [SP, #-0x10]!
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/* Save FPU registers (32 128-bits + 2 64-bits configuration and status registers) */
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STP Q0, Q1, [SP,#-0x20]!
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STP Q2, Q3, [SP,#-0x20]!
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STP Q4, Q5, [SP,#-0x20]!
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STP Q6, Q7, [SP,#-0x20]!
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STP Q8, Q9, [SP,#-0x20]!
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STP Q10, Q11, [SP,#-0x20]!
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STP Q12, Q13, [SP,#-0x20]!
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STP Q14, Q15, [SP,#-0x20]!
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STP Q16, Q17, [SP,#-0x20]!
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STP Q18, Q19, [SP,#-0x20]!
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STP Q20, Q21, [SP,#-0x20]!
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STP Q22, Q23, [SP,#-0x20]!
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|
STP Q24, Q25, [SP,#-0x20]!
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|
STP Q26, Q27, [SP,#-0x20]!
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|
STP Q28, Q29, [SP,#-0x20]!
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|
STP Q30, Q31, [SP,#-0x20]!
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|
|
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/* Even though upper 32 bits of FPSR and FPCR are reserved, save and restore the whole 64 bits to keep 16-byte SP alignement. */
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|
MRS X9, FPSR
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MRS X10, FPCR
|
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STP X9, X10, [SP, #-0x10]!
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|
|
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/* Call the C handler. */
|
|
BL vApplicationFPUSafeIRQHandler
|
|
|
|
/* Restore FPU registers */
|
|
|
|
LDP X9, X10, [SP], #0x10
|
|
LDP Q30, Q31, [SP], #0x20
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|
LDP Q28, Q29, [SP], #0x20
|
|
LDP Q26, Q27, [SP], #0x20
|
|
LDP Q24, Q25, [SP], #0x20
|
|
LDP Q22, Q23, [SP], #0x20
|
|
LDP Q20, Q21, [SP], #0x20
|
|
LDP Q18, Q19, [SP], #0x20
|
|
LDP Q16, Q17, [SP], #0x20
|
|
LDP Q14, Q15, [SP], #0x20
|
|
LDP Q12, Q13, [SP], #0x20
|
|
LDP Q10, Q11, [SP], #0x20
|
|
LDP Q8, Q9, [SP], #0x20
|
|
LDP Q6, Q7, [SP], #0x20
|
|
LDP Q4, Q5, [SP], #0x20
|
|
LDP Q2, Q3, [SP], #0x20
|
|
LDP Q0, Q1, [SP], #0x20
|
|
MSR FPSR, X9
|
|
MSR FPCR, X10
|
|
|
|
/* Restore FP and LR */
|
|
LDP X29, X30, [SP], #0x10
|
|
RET
|
|
|
|
.align 8
|
|
pxCurrentTCBConst: .dword pxCurrentTCB
|
|
ullCriticalNestingConst: .dword ullCriticalNesting
|
|
ullPortTaskHasFPUContextConst: .dword ullPortTaskHasFPUContext
|
|
|
|
ullMaxAPIPriorityMaskConst: .dword ullMaxAPIPriorityMask
|
|
ullPortInterruptNestingConst: .dword ullPortInterruptNesting
|
|
ullPortYieldRequiredConst: .dword ullPortYieldRequired
|
|
|
|
.end
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