mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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692 lines
26 KiB
C
692 lines
26 KiB
C
/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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/* Standard includes. */
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#include <stdlib.h>
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#include <string.h>
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
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#error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
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#endif
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#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
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#error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
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#endif
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#ifndef configUNIQUE_INTERRUPT_PRIORITIES
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#error configUNIQUE_INTERRUPT_PRIORITIES must be defined. Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
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#endif
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#ifndef configSETUP_TICK_INTERRUPT
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#error configSETUP_TICK_INTERRUPT() must be defined. Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
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#endif /* configSETUP_TICK_INTERRUPT */
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#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
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#error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
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#endif
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#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
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#error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
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#endif
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#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
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#error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
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#endif
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#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
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/* Check the configuration. */
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#if ( configMAX_PRIORITIES > 32 )
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#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
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#endif
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#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
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/* In case security extensions are implemented. */
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#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
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#error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
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#endif
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/*
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* __ARM_FP is defined by the c preprocessor when FPU support is enabled,
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* usually with the -mfpu= argument and -mfloat-abi=.
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*
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* Note: Some implementations of the c standard library may use FPU registers
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* for generic memory operations (memcpy, etc).
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* When setting configUSE_TASK_FPU_SUPPORT == 1, care must be taken to
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* ensure that the FPU registers are not used without an FPU context.
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*/
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#if ( configUSE_TASK_FPU_SUPPORT == 0 )
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#ifdef __ARM_FP
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#error __ARM_FP is defined, so configUSE_TASK_FPU_SUPPORT must be set to either to 1 or 2.
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#endif /* __ARM_FP */
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#elif ( configUSE_TASK_FPU_SUPPORT == 1 ) || ( configUSE_TASK_FPU_SUPPORT == 2 )
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#ifndef __ARM_FP
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#error __ARM_FP is not defined, so configUSE_TASK_FPU_SUPPORT must be set to 0.
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#endif /* __ARM_FP */
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#endif /* configUSE_TASK_FPU_SUPPORT */
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/*
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* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
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* portmacro.h.
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*/
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#ifndef configCLEAR_TICK_INTERRUPT
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#define configCLEAR_TICK_INTERRUPT()
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#endif
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/*
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* A critical section is exited when the critical section nesting count reaches
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* this value.
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*/
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#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
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/*
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* In all GICs 255 can be written to the priority mask register to unmask all
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* (but the lowest) interrupt priority.
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*/
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#define portUNMASK_VALUE ( 0xFFUL )
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/*
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* Tasks are not created with a floating point context, but can be given a
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* floating point context after they have been created. A variable is stored as
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* part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
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* does not have an FPU context, or any other value if the task does have an FPU
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* context.
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*/
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#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
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/* Constants required to setup the initial task context. */
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#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
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#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
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#define portINTERRUPT_ENABLE_BIT ( 0x80UL )
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#define portTHUMB_MODE_ADDRESS ( 0x01UL )
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/*
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* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
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* point is zero.
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*/
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#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
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/* Masks all bits in the APSR other than the mode bits. */
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#define portAPSR_MODE_BITS_MASK ( 0x1F )
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/* The value of the mode bits in the APSR when the CPU is executing in user
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* mode. */
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#define portAPSR_USER_MODE ( 0x10 )
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/* The critical section macros only mask interrupts up to an application
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* determined priority level. Sometimes it is necessary to turn interrupt off in
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* the CPU itself before modifying certain hardware registers. */
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#define portCPU_IRQ_DISABLE() \
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__asm volatile ( "CPSID i" ::: "memory" ); \
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__asm volatile ( "DSB" ); \
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__asm volatile ( "ISB" );
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#define portCPU_IRQ_ENABLE() \
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__asm volatile ( "CPSIE i" ::: "memory" ); \
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__asm volatile ( "DSB" ); \
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__asm volatile ( "ISB" );
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/* Macro to unmask all interrupt priorities. */
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#define portCLEAR_INTERRUPT_MASK() \
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{ \
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portCPU_IRQ_DISABLE(); \
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portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
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__asm volatile ( "DSB \n" \
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"ISB \n" ); \
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portCPU_IRQ_ENABLE(); \
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}
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#define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL
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#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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#define portBIT_0_SET ( ( uint8_t ) 0x01 )
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/*
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* Let the user override the pre-loading of the initial LR with the address of
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* prvTaskExitError() in case is messes up unwinding of the stack in the
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* debugger.
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*/
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#ifdef configTASK_RETURN_ADDRESS
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#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
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#else
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#define portTASK_RETURN_ADDRESS prvTaskExitError
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#endif
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#if ( configUSE_TASK_FPU_SUPPORT != 0 )
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/*
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* The space on the stack required to hold the FPU registers.
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*
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* The ARM Cortex R5 processor implements the VFPv3-D16 FPU
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* architecture. This includes only 16 double-precision registers,
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* instead of 32 as is in VFPv3. The register bank can be viewed
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* either as sixteen 64-bit double-word registers (D0-D15) or
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* thirty-two 32-bit single-word registers (S0-S31), in both cases
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* the size of the bank remains the same. The FPU has also a 32-bit
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* status register.
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*/
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#define portFPU_REGISTER_WORDS ( ( 16 * 2 ) + 1 )
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#endif /* configUSE_TASK_FPU_SUPPORT != 0 */
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/*-----------------------------------------------------------*/
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/*
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* Starts the first task executing. This function is necessarily written in
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* assembly code so is implemented in portASM.s.
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*/
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extern void vPortRestoreTaskContext( void );
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/*
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* Used to catch tasks that attempt to return from their implementing function.
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*/
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static void prvTaskExitError( void );
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#if ( configUSE_TASK_FPU_SUPPORT != 0 )
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/*
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* If the application provides an implementation of vApplicationIRQHandler(),
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* then it will get called directly without saving the FPU registers on
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* interrupt entry, and this weak implementation of
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* vApplicationFPUSafeIRQHandler() is just provided to remove linkage errors -
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* it should never actually get called so its implementation contains a
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* call to configASSERT() that will always fail.
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*
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* If the application provides its own implementation of
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* vApplicationFPUSafeIRQHandler() then the implementation of
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* vApplicationIRQHandler() provided in portASM.S will save the FPU registers
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* before calling it.
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*
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* Therefore, if the application writer wants FPU registers to be saved on
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* interrupt entry their IRQ handler must be called
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* vApplicationFPUSafeIRQHandler(), and if the application writer does not want
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* FPU registers to be saved on interrupt entry their IRQ handler must be
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* called vApplicationIRQHandler().
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*/
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void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) __attribute__( ( weak ) );
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#endif /* configUSE_TASK_FPU_SUPPORT != 0 */
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/*-----------------------------------------------------------*/
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/*
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* A variable is used to keep track of the critical section nesting. This
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* variable has to be stored as part of the task context and must be initialised to
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* a non zero value to ensure interrupts don't inadvertently become unmasked before
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* the scheduler starts. As it is stored as part of the task context it will
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* automatically be set to 0 when the first task is started.
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*/
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volatile uint32_t ulCriticalNesting = 9999UL;
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#if ( configUSE_TASK_FPU_SUPPORT != 0 )
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/*
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* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
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* a floating point context must be saved and restored for the task.
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*/
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uint32_t ulPortTaskHasFPUContext = pdFALSE;
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#endif /* configUSE_TASK_FPU_SUPPORT != 0 */
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/* Set to 1 to pend a context switch from an ISR. */
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uint32_t ulPortYieldRequired = pdFALSE;
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/*
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* Counts the interrupt nesting depth. A context switch is only performed if
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* if the nesting depth is 0.
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*/
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uint32_t ulPortInterruptNesting = 0UL;
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/* Used in asm code. */
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__attribute__( ( used ) ) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
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__attribute__( ( used ) ) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
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__attribute__( ( used ) ) const uint32_t ulICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
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__attribute__( ( used ) ) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
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/*-----------------------------------------------------------*/
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/*
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* See header file for description.
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*/
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StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
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TaskFunction_t pxCode,
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void * pvParameters )
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{
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/*
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* Setup the initial stack of the task. The stack is set exactly as
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* expected by the portRESTORE_CONTEXT() macro.
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*
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* The fist real value on the stack is the status register, which is set for
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* system mode, with interrupts enabled. A few NULLs are added first to ensure
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* GDB does not try decoding a non-existent return address.
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*/
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*pxTopOfStack = ( StackType_t ) NULL;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) NULL;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) NULL;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
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if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
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{
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/* The task will start in THUMB mode. */
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*pxTopOfStack |= portTHUMB_MODE_BIT;
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}
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pxTopOfStack--;
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/* Next the return address, which in this case is the start of the task. */
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*pxTopOfStack = ( StackType_t ) pxCode;
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pxTopOfStack--;
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/* Next all the registers other than the stack pointer. */
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*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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/*
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* The task will start with a critical nesting count of 0 as interrupts are
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* enabled.
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*/
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pxTopOfStack--;
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*pxTopOfStack = portNO_CRITICAL_NESTING;
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#if ( configUSE_TASK_FPU_SUPPORT == 1 )
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{
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/*
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* The task will start without a floating point context.
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* A task that uses the floating point hardware must call
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* vPortTaskUsesFPU() before executing any floating point
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* instructions.
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*/
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pxTopOfStack--;
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*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
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}
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#elif ( configUSE_TASK_FPU_SUPPORT == 2 )
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{
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/*
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* The task will start with a floating point context. Leave enough
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* space for the registers and ensure they are initialized to 0.
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*/
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pxTopOfStack -= portFPU_REGISTER_WORDS;
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memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) );
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pxTopOfStack--;
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*pxTopOfStack = pdTRUE;
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ulPortTaskHasFPUContext = pdTRUE;
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}
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#elif ( configUSE_TASK_FPU_SUPPORT != 0 )
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{
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#error Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 0, 1, or 2.
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}
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#endif /* configUSE_TASK_FPU_SUPPORT */
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return pxTopOfStack;
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}
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/*-----------------------------------------------------------*/
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static void prvTaskExitError( void )
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{
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/*
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* A function that implements a task must not exit or attempt to return to
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* its caller as there is nothing to return to. If a task wants to exit it
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* should instead call vTaskDelete( NULL ).
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*
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* Artificially force an assert() to be triggered if configASSERT() is
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* defined, then stop here so application writers can catch the error.
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*/
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configASSERT( ulPortInterruptNesting == ~0UL );
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portDISABLE_INTERRUPTS();
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for( ; ; )
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{
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}
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}
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/*-----------------------------------------------------------*/
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#if ( configUSE_TASK_FPU_SUPPORT != 0 )
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void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) /* __attribute__( ( weak ) ) */
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{
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( void ) ulICCIAR;
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configASSERT( ( volatile void * ) NULL );
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}
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#endif /* configUSE_TASK_FPU_SUPPORT != 0 */
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/*-----------------------------------------------------------*/
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BaseType_t xPortStartScheduler( void )
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{
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uint32_t ulAPSR, ulCycles = 8; /* 8 bits per byte. */
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#if ( configASSERT_DEFINED == 1 )
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{
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volatile uint8_t ucOriginalPriority;
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volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
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volatile uint8_t ucMaxPriorityValue;
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/*
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* Determine how many priority bits are implemented in the GIC.
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* Save the interrupt priority value that is about to be clobbered.
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*/
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ucOriginalPriority = *pucFirstUserPriorityRegister;
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/*
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* Determine the number of priority bits available. First write to
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* all possible bits.
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*/
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*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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/* Read the value back to see how many bits stuck. */
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ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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/* Shift to the least significant bits. */
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while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
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{
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ucMaxPriorityValue >>= ( uint8_t ) 0x01;
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/*
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* If ulCycles reaches 0 then ucMaxPriorityValue must have been
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* read as 0, indicating a misconfiguration.
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*/
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ulCycles--;
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if( ulCycles == 0 )
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{
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break;
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}
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}
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/*
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* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
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* value.
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*/
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configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );
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/*
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* Restore the clobbered interrupt priority register to its original
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* value.
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*/
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*pucFirstUserPriorityRegister = ucOriginalPriority;
|
|
}
|
|
#endif /* configASSERT_DEFINED */
|
|
|
|
/*
|
|
* Only continue if the CPU is not in User mode. The CPU must be in a
|
|
* Privileged mode for the scheduler to start.
|
|
*/
|
|
__asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR )::"memory" );
|
|
ulAPSR &= portAPSR_MODE_BITS_MASK;
|
|
configASSERT( ulAPSR != portAPSR_USER_MODE );
|
|
|
|
if( ulAPSR != portAPSR_USER_MODE )
|
|
{
|
|
/*
|
|
* Only continue if the binary point value is set to its lowest possible
|
|
* setting. See the comments in vPortValidateInterruptPriority() below for
|
|
* more information.
|
|
*/
|
|
configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
|
|
|
|
if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
|
|
{
|
|
/*
|
|
* Interrupts are turned off in the CPU itself to ensure tick does
|
|
* not execute while the scheduler is being started. Interrupts are
|
|
* automatically turned back on in the CPU when the first task starts
|
|
* executing.
|
|
*/
|
|
portCPU_IRQ_DISABLE();
|
|
|
|
/* Start the timer that generates the tick ISR. */
|
|
configSETUP_TICK_INTERRUPT();
|
|
|
|
/* Start the first task executing. */
|
|
vPortRestoreTaskContext();
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Will only get here if vTaskStartScheduler() was called with the CPU in
|
|
* a non-privileged mode or the binary point register was not set to its lowest
|
|
* possible value. prvTaskExitError() is referenced to prevent a compiler
|
|
* warning about it being defined but not referenced in the case that the user
|
|
* defines their own exit address.
|
|
*/
|
|
( void ) prvTaskExitError;
|
|
|
|
return 0;
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortEndScheduler( void )
|
|
{
|
|
/*
|
|
* Not implemented in ports where there is nothing to return to.
|
|
* Artificially force an assert.
|
|
*/
|
|
configASSERT( ulCriticalNesting == 1000UL );
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortEnterCritical( void )
|
|
{
|
|
/* Mask interrupts up to the max syscall interrupt priority. */
|
|
ulPortSetInterruptMask();
|
|
|
|
/*
|
|
* Now that interrupts are disabled, ulCriticalNesting can be accessed
|
|
* directly. Increment ulCriticalNesting to keep a count of how many times
|
|
* portENTER_CRITICAL() has been called.
|
|
*/
|
|
ulCriticalNesting++;
|
|
|
|
/*
|
|
* This is not the interrupt safe version of the enter critical function so
|
|
* assert() if it is being called from an interrupt context. Only API
|
|
* functions that end in "FromISR" can be used in an interrupt. Only assert if
|
|
* the critical nesting count is 1 to protect against recursive calls if the
|
|
* assert function also uses a critical section.
|
|
*/
|
|
if( ulCriticalNesting == 1 )
|
|
{
|
|
configASSERT( ulPortInterruptNesting == 0 );
|
|
}
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortExitCritical( void )
|
|
{
|
|
if( ulCriticalNesting > portNO_CRITICAL_NESTING )
|
|
{
|
|
/* Decrement the nesting count as the critical section is being exited. */
|
|
ulCriticalNesting--;
|
|
|
|
/*
|
|
* If the nesting level has reached zero then all interrupt
|
|
* priorities must be re-enabled.
|
|
*/
|
|
if( ulCriticalNesting == portNO_CRITICAL_NESTING )
|
|
{
|
|
/*
|
|
* Critical nesting has reached zero so all interrupt priorities
|
|
* should be unmasked.
|
|
*/
|
|
portCLEAR_INTERRUPT_MASK();
|
|
}
|
|
}
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void FreeRTOS_Tick_Handler( void )
|
|
{
|
|
/*
|
|
* Set interrupt mask before altering scheduler structures. The tick
|
|
* handler runs at the lowest priority, so interrupts cannot already be masked,
|
|
* so there is no need to save and restore the current mask value. It is
|
|
* necessary to turn off interrupts in the CPU itself while the ICCPMR is being
|
|
* updated.
|
|
*/
|
|
portCPU_IRQ_DISABLE();
|
|
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
|
|
__asm volatile ( "dsb \n"
|
|
"isb \n" ::: "memory" );
|
|
portCPU_IRQ_ENABLE();
|
|
|
|
/* Increment the RTOS tick. */
|
|
if( xTaskIncrementTick() != pdFALSE )
|
|
{
|
|
ulPortYieldRequired = pdTRUE;
|
|
}
|
|
|
|
/* Ensure all interrupt priorities are active again. */
|
|
portCLEAR_INTERRUPT_MASK();
|
|
configCLEAR_TICK_INTERRUPT();
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configUSE_TASK_FPU_SUPPORT == 1 )
|
|
|
|
void vPortTaskUsesFPU( void )
|
|
{
|
|
uint32_t ulInitialFPSCR = 0;
|
|
|
|
/*
|
|
* A task is registering the fact that it needs an FPU context. Set the
|
|
* FPU flag (which is saved as part of the task context).
|
|
*/
|
|
ulPortTaskHasFPUContext = pdTRUE;
|
|
|
|
/* Initialise the floating point status register. */
|
|
__asm volatile ( "FMXR FPSCR, %0" ::"r" ( ulInitialFPSCR ) : "memory" );
|
|
}
|
|
|
|
#endif /* configUSE_TASK_FPU_SUPPORT == 1 */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortClearInterruptMask( uint32_t ulNewMaskValue )
|
|
{
|
|
if( ulNewMaskValue == pdFALSE )
|
|
{
|
|
portCLEAR_INTERRUPT_MASK();
|
|
}
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
uint32_t ulPortSetInterruptMask( void )
|
|
{
|
|
uint32_t ulReturn;
|
|
|
|
/* Interrupts must be masked while ICCPMR is updated. */
|
|
portCPU_IRQ_DISABLE();
|
|
|
|
if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
|
|
{
|
|
/* Interrupts were already masked. */
|
|
ulReturn = pdTRUE;
|
|
}
|
|
else
|
|
{
|
|
ulReturn = pdFALSE;
|
|
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
|
|
__asm volatile ( "dsb \n"
|
|
"isb \n" ::: "memory" );
|
|
}
|
|
|
|
portCPU_IRQ_ENABLE();
|
|
|
|
return ulReturn;
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configASSERT_DEFINED == 1 )
|
|
|
|
void vPortValidateInterruptPriority( void )
|
|
{
|
|
/*
|
|
* The following assertion will fail if a service routine (ISR) for
|
|
* an interrupt that has been assigned a priority above
|
|
* configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
|
|
* function. ISR safe FreeRTOS API functions must *only* be called
|
|
* from interrupts that have been assigned a priority at or below
|
|
* configMAX_SYSCALL_INTERRUPT_PRIORITY.
|
|
*
|
|
* Numerically low interrupt priority numbers represent logically high
|
|
* interrupt priorities, therefore the priority of the interrupt must
|
|
* be set to a value equal to or numerically *higher* than
|
|
* configMAX_SYSCALL_INTERRUPT_PRIORITY.
|
|
*
|
|
* FreeRTOS maintains separate thread and ISR API functions to ensure
|
|
* interrupt entry is as fast and simple as possible.
|
|
*/
|
|
|
|
configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
|
|
|
|
/*
|
|
* Priority grouping: The interrupt controller (GIC) allows the bits
|
|
* that define each interrupt's priority to be split between bits that
|
|
* define the interrupt's pre-emption priority bits and bits that define
|
|
* the interrupt's sub-priority. For simplicity all bits must be defined
|
|
* to be pre-emption priority bits. The following assertion will fail if
|
|
* this is not the case (if some bits represent a sub-priority).
|
|
*
|
|
* The priority grouping is configured by the GIC's binary point register
|
|
* (ICCBPR). Writing 0 to ICCBPR will ensure it is set to its lowest
|
|
* possible value (which may be above 0).
|
|
*/
|
|
configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
|
|
}
|
|
|
|
#endif /* configASSERT_DEFINED */
|
|
/*-----------------------------------------------------------*/
|