mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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705 lines
58 KiB
C
705 lines
58 KiB
C
/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT AND BSD-3-Clause
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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/*This file has been prepared for Doxygen automatic documentation generation.*/
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/*! \file *********************************************************************
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*
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* \brief FreeRTOS port source for AVR32 UC3.
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*
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* - Compiler: GNU GCC for AVR32
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* - Supported devices: All AVR32 devices can be used.
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* - AppNote:
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*
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* \author Atmel Corporation (Now Microchip):
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* https://www.microchip.com \n
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* Support and FAQ: https://www.microchip.com/support/
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*
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*****************************************************************************/
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/*
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* Copyright (c) 2007, Atmel Corporation All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of ATMEL may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
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* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef PORTMACRO_H
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#define PORTMACRO_H
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/*-----------------------------------------------------------
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* Port specific definitions.
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*
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* The settings in this file configure FreeRTOS correctly for the
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* given hardware and compiler.
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*
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* These settings should not be altered.
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*-----------------------------------------------------------
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*/
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#include <avr32/io.h>
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#include "intc.h"
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#include "compiler.h"
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/* *INDENT-OFF* */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* *INDENT-ON* */
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/* Type definitions. */
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#define portCHAR char
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#define portFLOAT float
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#define portDOUBLE double
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#define portLONG long
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#define portSHORT short
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#define portSTACK_TYPE uint32_t
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#define portBASE_TYPE long
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typedef portSTACK_TYPE StackType_t;
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typedef long BaseType_t;
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typedef unsigned long UBaseType_t;
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#define TASK_DELAY_MS( x ) ( ( x ) / portTICK_PERIOD_MS )
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#define TASK_DELAY_S( x ) ( ( x ) * 1000 / portTICK_PERIOD_MS )
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#define TASK_DELAY_MIN( x ) ( ( x ) * 60 * 1000 / portTICK_PERIOD_MS )
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#define configTICK_TC_IRQ ATPASTE2( AVR32_TC_IRQ, configTICK_TC_CHANNEL )
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#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
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typedef uint16_t TickType_t;
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#define portMAX_DELAY ( TickType_t ) 0xffff
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#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
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typedef uint32_t TickType_t;
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#define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL )
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#else
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#error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
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#endif
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/*-----------------------------------------------------------*/
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/* Architecture specifics. */
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#define portSTACK_GROWTH ( -1 )
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#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
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#define portBYTE_ALIGNMENT 4
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#define portNOP() { __asm__ __volatile__ ( "nop" ); }
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/*-----------------------------------------------------------*/
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/*-----------------------------------------------------------*/
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/* INTC-specific. */
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#define DISABLE_ALL_EXCEPTIONS() Disable_global_exception()
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#define ENABLE_ALL_EXCEPTIONS() Enable_global_exception()
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#define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt()
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#define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt()
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#define DISABLE_INT_LEVEL( int_lev ) Disable_interrupt_level( int_lev )
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#define ENABLE_INT_LEVEL( int_lev ) Enable_interrupt_level( int_lev )
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/*
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* Debug trace.
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* Activated if and only if configDBG is nonzero.
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* Prints a formatted string to stdout.
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* The current source file name and line number are output with a colon before
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* the formatted string.
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* A carriage return and a linefeed are appended to the output.
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* stdout is redirected to the USART configured by configDBG_USART.
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* The parameters are the same as for the standard printf function.
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* There is no return value.
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* SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc,
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* which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock.
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*/
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#if configDBG
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#define portDBG_TRACE( ... ) \
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{ \
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fputs( __FILE__ ":" ASTRINGZ( __LINE__ ) ": ", stdout ); \
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printf( __VA_ARGS__ ); \
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fputs( "\r\n", stdout ); \
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}
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#else
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#define portDBG_TRACE( ... )
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#endif
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/* Critical section management. */
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#define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS()
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#define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS()
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extern void vPortEnterCritical( void );
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extern void vPortExitCritical( void );
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#define portENTER_CRITICAL() vPortEnterCritical();
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#define portEXIT_CRITICAL() vPortExitCritical();
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/* Added as there is no such function in FreeRTOS. */
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extern void * pvPortRealloc( void * pv,
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size_t xSize );
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/*-----------------------------------------------------------*/
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/*=============================================================================================*/
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/*
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* Restore Context for cases other than INTi.
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*/
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#define portRESTORE_CONTEXT() \
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{ \
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extern volatile uint32_t ulCriticalNesting; \
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extern volatile void * volatile pxCurrentTCB; \
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\
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__asm__ __volatile__ ( \
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/* Set SP to point to new stack */ \
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"mov r8, LO(%[pxCurrentTCB]) \n\t" \
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"orh r8, HI(%[pxCurrentTCB]) \n\t" \
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"ld.w r0, r8[0] \n\t" \
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"ld.w sp, r0[0] \n\t" \
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\
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/* Restore ulCriticalNesting variable */ \
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"ld.w r0, sp++ \n\t" \
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"mov r8, LO(%[ulCriticalNesting]) \n\t" \
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"orh r8, HI(%[ulCriticalNesting]) \n\t" \
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"st.w r8[0], r0 \n\t" \
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\
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/* Restore R0..R7 */ \
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"ldm sp++, r0-r7 \n\t" \
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/* R0-R7 should not be used below this line */ \
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/* Skip PC and SR (will do it at the end) */ \
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"sub sp, -2*4 \n\t" \
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/* Restore R8..R12 and LR */ \
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"ldm sp++, r8-r12, lr \n\t" \
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/* Restore SR */ \
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"ld.w r0, sp[-8*4]\n\t" /* R0 is modified, is restored later. */ \
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"mtsr %[SR], r0 \n\t" \
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/* Restore r0 */ \
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"ld.w r0, sp[-9*4] \n\t" \
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/* Restore PC */ \
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"ld.w pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */ \
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: \
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:[ ulCriticalNesting ] "i" ( &ulCriticalNesting ), \
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[ pxCurrentTCB ] "i" ( &pxCurrentTCB ), \
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[ SR ] "i" ( AVR32_SR ) \
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); \
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}
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/*
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* portSAVE_CONTEXT_INT() and portRESTORE_CONTEXT_INT(): for INT0..3 exceptions.
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* portSAVE_CONTEXT_SCALL() and portRESTORE_CONTEXT_SCALL(): for the scall exception.
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*
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* Had to make different versions because registers saved on the system stack
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* are not the same between INT0..3 exceptions and the scall exception.
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*/
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/* Task context stack layout: */
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/* R8 (*) */
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/* R9 (*) */
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/* R10 (*) */
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/* R11 (*) */
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/* R12 (*) */
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/* R14/LR (*) */
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/* R15/PC (*) */
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/* SR (*) */
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/* R0 */
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/* R1 */
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/* R2 */
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/* R3 */
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/* R4 */
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/* R5 */
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/* R6 */
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/* R7 */
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/* ulCriticalNesting */
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/* (*) automatically done for INT0..INT3, but not for SCALL */
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/*
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* The ISR used for the scheduler tick depends on whether the cooperative or
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* the preemptive scheduler is being used.
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*/
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#if configUSE_PREEMPTION == 0
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/*
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* portSAVE_CONTEXT_OS_INT() for OS Tick exception.
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*/
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#define portSAVE_CONTEXT_OS_INT() \
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{ \
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/* Save R0..R7 */ \
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__asm__ __volatile__ ( "stm --sp, r0-r7" ); \
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\
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/* With the cooperative scheduler, as there is no context switch by interrupt, */ \
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/* there is also no context save. */ \
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}
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/*
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* portRESTORE_CONTEXT_OS_INT() for Tick exception.
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*/
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#define portRESTORE_CONTEXT_OS_INT() \
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{ \
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__asm__ __volatile__ ( \
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/* Restore R0..R7 */ \
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"ldm sp++, r0-r7\n\t" \
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\
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/* With the cooperative scheduler, as there is no context switch by interrupt, */ \
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/* there is also no context restore. */ \
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"rete" \
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); \
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}
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#else /* if configUSE_PREEMPTION == 0 */
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/*
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* portSAVE_CONTEXT_OS_INT() for OS Tick exception.
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*/
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#define portSAVE_CONTEXT_OS_INT() \
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{ \
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extern volatile uint32_t ulCriticalNesting; \
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extern volatile void * volatile pxCurrentTCB; \
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\
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/* When we come here */ \
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/* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
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\
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__asm__ __volatile__ ( \
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/* Save R0..R7 */ \
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"stm --sp, r0-r7 \n\t" \
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\
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/* Save ulCriticalNesting variable - R0 is overwritten */ \
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"mov r8, LO(%[ulCriticalNesting])\n\t" \
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"orh r8, HI(%[ulCriticalNesting])\n\t" \
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"ld.w r0, r8[0] \n\t" \
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"st.w --sp, r0 \n\t" \
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\
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/* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
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/* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
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/* level and allow other lower interrupt level to occur). */ \
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/* In this case we don't want to do a task switch because we don't know what the stack */ \
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/* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
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/* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
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/* will just be restoring the interrupt handler, no way!!! */ \
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/* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
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"ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \
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"bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \
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"cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \
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"brhi LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE] \n\t" \
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\
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/* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
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/* NOTE: we don't enter a critical section here because all interrupt handlers */ \
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/* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */ \
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/* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */ \
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/* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */ \
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"mov r8, LO(%[pxCurrentTCB])\n\t" \
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"orh r8, HI(%[pxCurrentTCB])\n\t" \
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"ld.w r0, r8[0]\n\t" \
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"st.w r0[0], sp\n" \
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\
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"LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE]:" \
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: \
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:[ ulCriticalNesting ] "i" ( &ulCriticalNesting ), \
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[ pxCurrentTCB ] "i" ( &pxCurrentTCB ), \
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[ LINE ] "i" ( __LINE__ ) \
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); \
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}
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/*
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* portRESTORE_CONTEXT_OS_INT() for Tick exception.
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*/
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#define portRESTORE_CONTEXT_OS_INT() \
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{ \
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extern volatile uint32_t ulCriticalNesting; \
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extern volatile void * volatile pxCurrentTCB; \
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\
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/* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
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/* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
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/* level and allow other lower interrupt level to occur). */ \
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/* In this case we don't want to do a task switch because we don't know what the stack */ \
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/* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
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/* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
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/* will just be restoring the interrupt handler, no way!!! */ \
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__asm__ __volatile__ ( \
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"ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \
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"bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \
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"cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \
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"brhi LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]" \
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: \
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:[ LINE ] "i" ( __LINE__ ) \
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); \
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\
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/* Else */ \
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/* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */ \
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/* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \
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portENTER_CRITICAL(); \
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vTaskSwitchContext(); \
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portEXIT_CRITICAL(); \
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\
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/* Restore all registers */ \
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\
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__asm__ __volatile__ ( \
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/* Set SP to point to new stack */ \
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"mov r8, LO(%[pxCurrentTCB]) \n\t" \
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"orh r8, HI(%[pxCurrentTCB]) \n\t" \
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"ld.w r0, r8[0] \n\t" \
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"ld.w sp, r0[0] \n" \
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\
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"LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t" \
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\
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/* Restore ulCriticalNesting variable */ \
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"ld.w r0, sp++ \n\t" \
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"mov r8, LO(%[ulCriticalNesting]) \n\t" \
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"orh r8, HI(%[ulCriticalNesting]) \n\t" \
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"st.w r8[0], r0 \n\t" \
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\
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/* Restore R0..R7 */ \
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"ldm sp++, r0-r7 \n\t" \
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\
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/* Now, the stack should be R8..R12, LR, PC and SR */ \
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"rete" \
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: \
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:[ ulCriticalNesting ] "i" ( &ulCriticalNesting ), \
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[ pxCurrentTCB ] "i" ( &pxCurrentTCB ), \
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[ LINE ] "i" ( __LINE__ ) \
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); \
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}
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#endif /* if configUSE_PREEMPTION == 0 */
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/*
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* portSAVE_CONTEXT_SCALL() for SupervisorCALL exception.
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*
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* NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode.
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*
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*/
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#define portSAVE_CONTEXT_SCALL() \
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{ \
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extern volatile uint32_t ulCriticalNesting; \
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extern volatile void * volatile pxCurrentTCB; \
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\
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/* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \
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/* If SR[M2:M0] == 001 */ \
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/* PC and SR are on the stack. */ \
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/* Else (other modes) */ \
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/* Nothing on the stack. */ \
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\
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/* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \
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/* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \
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/* in an interrupt|exception handler. */ \
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\
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__asm__ __volatile__ ( \
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/* in order to save R0-R7 */ \
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"sub sp, 6*4 \n\t" \
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/* Save R0..R7 */ \
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"stm --sp, r0-r7 \n\t" \
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\
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/* in order to save R8-R12 and LR */ \
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/* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
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"sub r7, sp,-16*4 \n\t" \
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/* Copy PC and SR in other places in the stack. */ \
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"ld.w r0, r7[-2*4] \n\t" /* Read SR */ \
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"st.w r7[-8*4], r0 \n\t" /* Copy SR */ \
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"ld.w r0, r7[-1*4] \n\t" /* Read PC */ \
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"st.w r7[-7*4], r0 \n\t" /* Copy PC */ \
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\
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/* Save R8..R12 and LR on the stack. */ \
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"stm --r7, r8-r12, lr \n\t" \
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\
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/* Arriving here we have the following stack organizations: */ \
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/* R8..R12, LR, PC, SR, R0..R7. */ \
|
|
\
|
|
/* Now we can finalize the save. */ \
|
|
\
|
|
/* Save ulCriticalNesting variable - R0 is overwritten */ \
|
|
"mov r8, LO(%[ulCriticalNesting]) \n\t" \
|
|
"orh r8, HI(%[ulCriticalNesting]) \n\t" \
|
|
"ld.w r0, r8[0] \n\t" \
|
|
"st.w --sp, r0" \
|
|
: \
|
|
:[ ulCriticalNesting ] "i" ( &ulCriticalNesting ) \
|
|
); \
|
|
\
|
|
/* Disable the its which may cause a context switch (i.e. cause a change of */ \
|
|
/* pxCurrentTCB). */ \
|
|
/* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \
|
|
/* critical section because it is a global structure. */ \
|
|
portENTER_CRITICAL(); \
|
|
\
|
|
/* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
|
|
__asm__ __volatile__ ( \
|
|
"mov r8, LO(%[pxCurrentTCB]) \n\t" \
|
|
"orh r8, HI(%[pxCurrentTCB]) \n\t" \
|
|
"ld.w r0, r8[0] \n\t" \
|
|
"st.w r0[0], sp" \
|
|
: \
|
|
:[ pxCurrentTCB ] "i" ( &pxCurrentTCB ) \
|
|
); \
|
|
}
|
|
|
|
/*
|
|
* portRESTORE_CONTEXT() for SupervisorCALL exception.
|
|
*/
|
|
#define portRESTORE_CONTEXT_SCALL() \
|
|
{ \
|
|
extern volatile uint32_t ulCriticalNesting; \
|
|
extern volatile void * volatile pxCurrentTCB; \
|
|
\
|
|
/* Restore all registers */ \
|
|
\
|
|
/* Set SP to point to new stack */ \
|
|
__asm__ __volatile__ ( \
|
|
"mov r8, LO(%[pxCurrentTCB]) \n\t" \
|
|
"orh r8, HI(%[pxCurrentTCB]) \n\t" \
|
|
"ld.w r0, r8[0] \n\t" \
|
|
"ld.w sp, r0[0]" \
|
|
: \
|
|
:[ pxCurrentTCB ] "i" ( &pxCurrentTCB ) \
|
|
); \
|
|
\
|
|
/* Leave pxCurrentTCB variable access critical section */ \
|
|
portEXIT_CRITICAL(); \
|
|
\
|
|
__asm__ __volatile__ ( \
|
|
/* Restore ulCriticalNesting variable */ \
|
|
"ld.w r0, sp++ \n\t" \
|
|
"mov r8, LO(%[ulCriticalNesting]) \n\t" \
|
|
"orh r8, HI(%[ulCriticalNesting]) \n\t" \
|
|
"st.w r8[0], r0 \n\t" \
|
|
\
|
|
/* skip PC and SR */ \
|
|
/* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
|
|
"sub r7, sp, -10*4 \n\t" \
|
|
/* Restore r8-r12 and LR */ \
|
|
"ldm r7++, r8-r12, lr \n\t" \
|
|
\
|
|
/* RETS will take care of the extra PC and SR restore. */ \
|
|
/* So, we have to prepare the stack for this. */ \
|
|
"ld.w r0, r7[-8*4] \n\t" /* Read SR */ \
|
|
"st.w r7[-2*4], r0 \n\t" /* Copy SR */ \
|
|
"ld.w r0, r7[-7*4] \n\t" /* Read PC */ \
|
|
"st.w r7[-1*4], r0 \n\t" /* Copy PC */ \
|
|
\
|
|
/* Restore R0..R7 */ \
|
|
"ldm sp++, r0-r7 \n\t" \
|
|
\
|
|
"sub sp, -6*4 \n\t" \
|
|
\
|
|
"rets" \
|
|
: \
|
|
:[ ulCriticalNesting ] "i" ( &ulCriticalNesting ) \
|
|
); \
|
|
}
|
|
|
|
|
|
/*
|
|
* The ISR used depends on whether the cooperative or
|
|
* the preemptive scheduler is being used.
|
|
*/
|
|
#if configUSE_PREEMPTION == 0
|
|
|
|
/*
|
|
* ISR entry and exit macros. These are only required if a task switch
|
|
* is required from the ISR.
|
|
*/
|
|
#define portENTER_SWITCHING_ISR() \
|
|
{ \
|
|
/* Save R0..R7 */ \
|
|
__asm__ __volatile__ ( "stm --sp, r0-r7" ); \
|
|
\
|
|
/* With the cooperative scheduler, as there is no context switch by interrupt, */ \
|
|
/* there is also no context save. */ \
|
|
}
|
|
|
|
/*
|
|
* Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
|
|
*/
|
|
#define portEXIT_SWITCHING_ISR() \
|
|
{ \
|
|
__asm__ __volatile__ ( \
|
|
/* Restore R0..R7 */ \
|
|
"ldm sp++, r0-r7 \n\t" \
|
|
\
|
|
/* With the cooperative scheduler, as there is no context switch by interrupt, */ \
|
|
/* there is also no context restore. */ \
|
|
"rete" \
|
|
); \
|
|
}
|
|
|
|
#else /* if configUSE_PREEMPTION == 0 */
|
|
|
|
/*
|
|
* ISR entry and exit macros. These are only required if a task switch
|
|
* is required from the ISR.
|
|
*/
|
|
#define portENTER_SWITCHING_ISR() \
|
|
{ \
|
|
extern volatile uint32_t ulCriticalNesting; \
|
|
extern volatile void * volatile pxCurrentTCB; \
|
|
\
|
|
/* When we come here */ \
|
|
/* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
|
|
\
|
|
__asm__ __volatile__ ( \
|
|
/* Save R0..R7 */ \
|
|
"stm --sp, r0-r7 \n\t" \
|
|
\
|
|
/* Save ulCriticalNesting variable - R0 is overwritten */ \
|
|
"mov r8, LO(%[ulCriticalNesting]) \n\t" \
|
|
"orh r8, HI(%[ulCriticalNesting]) \n\t" \
|
|
"ld.w r0, r8[0] \n\t" \
|
|
"st.w --sp, r0 \n\t" \
|
|
\
|
|
/* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
|
|
/* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
|
|
/* level and allow other lower interrupt level to occur). */ \
|
|
/* In this case we don't want to do a task switch because we don't know what the stack */ \
|
|
/* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
|
|
/* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
|
|
/* will just be restoring the interrupt handler, no way!!! */ \
|
|
/* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
|
|
"ld.w r0, sp[9*4] \n\t" /* Read SR in stack */ \
|
|
"bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */ \
|
|
"cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */ \
|
|
"brhi LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE] \n\t" \
|
|
\
|
|
/* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
|
|
"mov r8, LO(%[pxCurrentTCB]) \n\t" \
|
|
"orh r8, HI(%[pxCurrentTCB]) \n\t" \
|
|
"ld.w r0, r8[0] \n\t" \
|
|
"st.w r0[0], sp \n" \
|
|
\
|
|
"LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]:" \
|
|
: \
|
|
:[ ulCriticalNesting ] "i" ( &ulCriticalNesting ), \
|
|
[ pxCurrentTCB ] "i" ( &pxCurrentTCB ), \
|
|
[ LINE ] "i" ( __LINE__ ) \
|
|
); \
|
|
}
|
|
|
|
/*
|
|
* Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
|
|
*/
|
|
#define portEXIT_SWITCHING_ISR() \
|
|
{ \
|
|
extern volatile uint32_t ulCriticalNesting; \
|
|
extern volatile void * volatile pxCurrentTCB; \
|
|
\
|
|
__asm__ __volatile__ ( \
|
|
/* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
|
|
/* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
|
|
/* level and allow other lower interrupt level to occur). */ \
|
|
/* In this case it's of no use to switch context and restore a new SP because we purposely */ \
|
|
/* did not previously save SP in its TCB. */ \
|
|
"ld.w r0, sp[9*4] \n\t" /* Read SR in stack */ \
|
|
"bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */ \
|
|
"cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */ \
|
|
"brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE] \n\t" \
|
|
\
|
|
/* If a switch is required then we just need to call */ \
|
|
/* vTaskSwitchContext() as the context has already been */ \
|
|
/* saved. */ \
|
|
"cp.w r12, 1 \n\t" /* Check if Switch context is required. */ \
|
|
"brne LABEL_ISR_RESTORE_CONTEXT_%[LINE]" \
|
|
: \
|
|
:[ LINE ] "i" ( __LINE__ ) \
|
|
); \
|
|
\
|
|
/* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \
|
|
portENTER_CRITICAL(); \
|
|
vTaskSwitchContext(); \
|
|
portEXIT_CRITICAL(); \
|
|
\
|
|
__asm__ __volatile__ ( \
|
|
"LABEL_ISR_RESTORE_CONTEXT_%[LINE]: \n\t" \
|
|
/* Restore the context of which ever task is now the highest */ \
|
|
/* priority that is ready to run. */ \
|
|
\
|
|
/* Restore all registers */ \
|
|
\
|
|
/* Set SP to point to new stack */ \
|
|
"mov r8, LO(%[pxCurrentTCB]) \n\t" \
|
|
"orh r8, HI(%[pxCurrentTCB]) \n\t" \
|
|
"ld.w r0, r8[0] \n\t" \
|
|
"ld.w sp, r0[0] \n" \
|
|
\
|
|
"LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t" \
|
|
\
|
|
/* Restore ulCriticalNesting variable */ \
|
|
"ld.w r0, sp++ \n\t" \
|
|
"mov r8, LO(%[ulCriticalNesting]) \n\t" \
|
|
"orh r8, HI(%[ulCriticalNesting]) \n\t" \
|
|
"st.w r8[0], r0 \n\t" \
|
|
\
|
|
/* Restore R0..R7 */ \
|
|
"ldm sp++, r0-r7 \n\t" \
|
|
\
|
|
/* Now, the stack should be R8..R12, LR, PC and SR */ \
|
|
"rete" \
|
|
: \
|
|
:[ ulCriticalNesting ] "i" ( &ulCriticalNesting ), \
|
|
[ pxCurrentTCB ] "i" ( &pxCurrentTCB ), \
|
|
[ LINE ] "i" ( __LINE__ ) \
|
|
); \
|
|
}
|
|
|
|
#endif /* if configUSE_PREEMPTION == 0 */
|
|
|
|
|
|
#define portYIELD() { __asm__ __volatile__ ( "scall" ); }
|
|
|
|
/* Task function macros as described on the FreeRTOS.org WEB site. */
|
|
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
|
|
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
|
|
|
|
/* *INDENT-OFF* */
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
/* *INDENT-ON* */
|
|
|
|
#endif /* PORTMACRO_H */
|