mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-11-04 11:09:01 +01:00
689 lines
23 KiB
C
689 lines
23 KiB
C
/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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/* Standard includes. */
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#include <limits.h>
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
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/* Check the configuration. */
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#if ( configMAX_PRIORITIES > 32 )
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#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
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#endif
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#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
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#if ( configISR_STACK_SIZE < ( configMINIMAL_STACK_SIZE * 2 ) )
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#warning configISR_STACK_SIZE is probably too small!
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#endif /* ( configISR_STACK_SIZE < configMINIMAL_STACK_SIZE * 2 ) */
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#if ( ( configMAX_API_CALL_INTERRUPT_PRIORITY > portMAX_PRIORITY ) || ( configMAX_API_CALL_INTERRUPT_PRIORITY < 2 ) )
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#error configMAX_API_CALL_INTERRUPT_PRIORITY must be between 2 and 15
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#endif
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#if ( ( configSUPPORT_FPU == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) )
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#error configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 to use this port with an FPU
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#endif
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/* A critical section is exited when the critical section nesting count reaches
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* this value. */
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#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
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/* Tasks are not created with a floating point context, but can be given a
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* floating point context after they have been created. A variable is stored as
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* part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
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* does not have an FPU context, or any other value if the task does have an FPU
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* context. */
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#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
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/* Only the IF bit is set so tasks start with interrupts enabled. */
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#define portINITIAL_EFLAGS ( 0x200UL )
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/* Error interrupts are at the highest priority vectors. */
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#define portAPIC_LVT_ERROR_VECTOR ( 0xfe )
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#define portAPIC_SPURIOUS_INT_VECTOR ( 0xff )
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/* EFLAGS bits. */
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#define portEFLAGS_IF ( 0x200UL )
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/* FPU context size if FSAVE is used. */
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#define portFPU_CONTEXT_SIZE_BYTES 108
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/* The expected size of each entry in the IDT. Used to check structure packing
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* is set correctly. */
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#define portEXPECTED_IDT_ENTRY_SIZE 8
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/* Default flags setting for entries in the IDT. */
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#define portIDT_FLAGS ( 0x8E )
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/* This is the lowest possible ISR vector available to application code. */
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#define portAPIC_MIN_ALLOWABLE_VECTOR ( 0x20 )
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/* If configASSERT() is defined then the system stack is filled with this value
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* to allow for a crude stack overflow check. */
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#define portSTACK_WORD ( 0xecececec )
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/*-----------------------------------------------------------*/
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/*
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* Starts the first task executing.
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*/
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extern void vPortStartFirstTask( void );
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/*
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* Used to catch tasks that attempt to return from their implementing function.
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*/
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static void prvTaskExitError( void );
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/*
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* Complete one descriptor in the IDT.
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*/
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static void prvSetInterruptGate( uint8_t ucNumber,
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ISR_Handler_t pxHandlerFunction,
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uint8_t ucFlags );
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/*
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* The default handler installed in each IDT position.
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*/
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extern void vPortCentralInterruptWrapper( void );
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/*
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* Handler for portYIELD().
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*/
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extern void vPortYieldCall( void );
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/*
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* Configure the APIC to generate the RTOS tick.
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*/
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static void prvSetupTimerInterrupt( void );
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/*
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* Tick interrupt handler.
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*/
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extern void vPortTimerHandler( void );
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/*
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* Check an interrupt vector is not too high, too low, in use by FreeRTOS, or
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* already in use by the application.
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*/
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static BaseType_t prvCheckValidityOfVectorNumber( uint32_t ulVectorNumber );
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/*-----------------------------------------------------------*/
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/* A variable is used to keep track of the critical section nesting. This
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* variable must be initialised to a non zero value to ensure interrupts don't
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* inadvertently become unmasked before the scheduler starts. It is set to zero
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* before the first task starts executing. */
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volatile uint32_t ulCriticalNesting = 9999UL;
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/* A structure used to map the various fields of an IDT entry into separate
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* structure members. */
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struct IDTEntry
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{
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uint16_t usISRLow; /* Low 16 bits of handler address. */
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uint16_t usSegmentSelector; /* Flat model means this is not changed. */
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uint8_t ucZero; /* Must be set to zero. */
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uint8_t ucFlags; /* Flags for this entry. */
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uint16_t usISRHigh; /* High 16 bits of handler address. */
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}
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__attribute__( ( packed ) );
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typedef struct IDTEntry IDTEntry_t;
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/* Use to pass the location of the IDT to the CPU. */
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struct IDTPointer
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{
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uint16_t usTableLimit;
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uint32_t ulTableBase; /* The address of the first entry in xInterruptDescriptorTable. */
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}
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__attribute__( ( __packed__ ) );
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typedef struct IDTPointer IDTPointer_t;
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/* The IDT itself. */
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static __attribute__( ( aligned( 32 ) ) ) IDTEntry_t xInterruptDescriptorTable[ portNUM_VECTORS ];
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#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
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/* A table in which application defined interrupt handlers are stored. These
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* are called by the central interrupt handler if a common interrupt entry
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* point it used. */
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static ISR_Handler_t xInterruptHandlerTable[ portNUM_VECTORS ] = { NULL };
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#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
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#if ( configSUPPORT_FPU == 1 )
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/* Saved as part of the task context. If pucPortTaskFPUContextBuffer is NULL
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* then the task does not have an FPU context. If pucPortTaskFPUContextBuffer is
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* not NULL then it points to a buffer into which the FPU context can be saved. */
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uint8_t * pucPortTaskFPUContextBuffer __attribute__( ( used ) ) = pdFALSE;
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#endif /* configSUPPORT_FPU */
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/* The stack used by interrupt handlers. */
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static uint32_t ulSystemStack[ configISR_STACK_SIZE ] __attribute__( ( used ) ) = { 0 };
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/* Don't use the very top of the system stack so the return address
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* appears as 0 if the debugger tries to unwind the stack. */
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volatile uint32_t ulTopOfSystemStack __attribute__( ( used ) ) = ( uint32_t ) &( ulSystemStack[ configISR_STACK_SIZE - 5 ] );
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/* If a yield is requested from an interrupt or from a critical section then
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* the yield is not performed immediately, and ulPortYieldPending is set to pdTRUE
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* instead to indicate the yield should be performed at the end of the interrupt
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* when the critical section is exited. */
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volatile uint32_t ulPortYieldPending __attribute__( ( used ) ) = pdFALSE;
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/* Counts the interrupt nesting depth. Used to know when to switch to the
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* interrupt/system stack and when to save/restore a complete context. */
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volatile uint32_t ulInterruptNesting __attribute__( ( used ) ) = 0;
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/*-----------------------------------------------------------*/
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/*
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* See header file for description.
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*/
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StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
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TaskFunction_t pxCode,
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void * pvParameters )
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{
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uint32_t ulCodeSegment;
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/* Setup the initial stack as expected by the portFREERTOS_INTERRUPT_EXIT macro. */
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*pxTopOfStack = 0x00;
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pxTopOfStack--;
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*pxTopOfStack = 0x00;
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pxTopOfStack--;
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/* Parameters first. */
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*pxTopOfStack = ( StackType_t ) pvParameters;
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pxTopOfStack--;
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/* There is nothing to return to so assert if attempting to use the return
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* address. */
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*pxTopOfStack = ( StackType_t ) prvTaskExitError;
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pxTopOfStack--;
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/* iret used to start the task pops up to here. */
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*pxTopOfStack = portINITIAL_EFLAGS;
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pxTopOfStack--;
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/* CS */
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__asm volatile ( "movl %%cs, %0" : "=r" ( ulCodeSegment ) );
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*pxTopOfStack = ulCodeSegment;
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pxTopOfStack--;
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/* First instruction in the task. */
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*pxTopOfStack = ( StackType_t ) pxCode;
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pxTopOfStack--;
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/* General purpose registers as expected by a POPA instruction. */
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*pxTopOfStack = 0xEA;
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pxTopOfStack--;
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*pxTopOfStack = 0xEC;
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pxTopOfStack--;
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*pxTopOfStack = 0xED1; /* EDX */
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pxTopOfStack--;
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*pxTopOfStack = 0xEB1; /* EBX */
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pxTopOfStack--;
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/* Hole for ESP. */
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pxTopOfStack--;
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*pxTopOfStack = 0x00; /* EBP */
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pxTopOfStack--;
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*pxTopOfStack = 0xE5; /* ESI */
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pxTopOfStack--;
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*pxTopOfStack = 0xeeeeeeee; /* EDI */
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#if ( configSUPPORT_FPU == 1 )
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{
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pxTopOfStack--;
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/* Buffer for FPU context, which is initialised to NULL as tasks are not
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* created with an FPU context. */
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*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
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}
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#endif /* configSUPPORT_FPU */
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return pxTopOfStack;
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}
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/*-----------------------------------------------------------*/
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static void prvSetInterruptGate( uint8_t ucNumber,
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ISR_Handler_t pxHandlerFunction,
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uint8_t ucFlags )
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{
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uint16_t usCodeSegment;
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uint32_t ulBase = ( uint32_t ) pxHandlerFunction;
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xInterruptDescriptorTable[ ucNumber ].usISRLow = ( uint16_t ) ( ulBase & USHRT_MAX );
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xInterruptDescriptorTable[ ucNumber ].usISRHigh = ( uint16_t ) ( ( ulBase >> 16UL ) & USHRT_MAX );
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/* When the flat model is used the CS will never change. */
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__asm volatile ( "mov %%cs, %0" : "=r" ( usCodeSegment ) );
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xInterruptDescriptorTable[ ucNumber ].usSegmentSelector = usCodeSegment;
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xInterruptDescriptorTable[ ucNumber ].ucZero = 0;
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xInterruptDescriptorTable[ ucNumber ].ucFlags = ucFlags;
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}
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/*-----------------------------------------------------------*/
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void vPortSetupIDT( void )
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{
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uint32_t ulNum;
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IDTPointer_t xIDT;
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#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
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{
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for( ulNum = 0; ulNum < portNUM_VECTORS; ulNum++ )
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{
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/* If a handler has not already been installed on this vector. */
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if( ( xInterruptDescriptorTable[ ulNum ].usISRLow == 0x00 ) && ( xInterruptDescriptorTable[ ulNum ].usISRHigh == 0x00 ) )
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{
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prvSetInterruptGate( ( uint8_t ) ulNum, vPortCentralInterruptWrapper, portIDT_FLAGS );
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}
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}
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}
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#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
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/* Set IDT address. */
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xIDT.ulTableBase = ( uint32_t ) xInterruptDescriptorTable;
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xIDT.usTableLimit = sizeof( xInterruptDescriptorTable ) - 1;
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/* Set IDT in CPU. */
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__asm volatile ( "lidt %0" ::"m" ( xIDT ) );
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}
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/*-----------------------------------------------------------*/
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static void prvTaskExitError( void )
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{
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/* A function that implements a task must not exit or attempt to return to
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* its caller as there is nothing to return to. If a task wants to exit it
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* should instead call vTaskDelete( NULL ).
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*
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* Artificially force an assert() to be triggered if configASSERT() is
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* defined, then stop here so application writers can catch the error. */
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configASSERT( ulCriticalNesting == ~0UL );
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portDISABLE_INTERRUPTS();
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for( ; ; )
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{
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}
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}
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/*-----------------------------------------------------------*/
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static void prvSetupTimerInterrupt( void )
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{
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extern void vPortAPICErrorHandlerWrapper( void );
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extern void vPortAPICSpuriousHandler( void );
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/* Initialise LAPIC to a well known state. */
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portAPIC_LDR = 0xFFFFFFFF;
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portAPIC_LDR = ( ( portAPIC_LDR & 0x00FFFFFF ) | 0x00000001 );
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portAPIC_LVT_TIMER = portAPIC_DISABLE;
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portAPIC_LVT_PERF = portAPIC_NMI;
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portAPIC_LVT_LINT0 = portAPIC_DISABLE;
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portAPIC_LVT_LINT1 = portAPIC_DISABLE;
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portAPIC_TASK_PRIORITY = 0;
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/* Install APIC timer ISR vector. */
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prvSetInterruptGate( ( uint8_t ) portAPIC_TIMER_INT_VECTOR, vPortTimerHandler, portIDT_FLAGS );
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/* Install API error handler. */
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prvSetInterruptGate( ( uint8_t ) portAPIC_LVT_ERROR_VECTOR, vPortAPICErrorHandlerWrapper, portIDT_FLAGS );
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/* Install Yield handler. */
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prvSetInterruptGate( ( uint8_t ) portAPIC_YIELD_INT_VECTOR, vPortYieldCall, portIDT_FLAGS );
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/* Install spurious interrupt vector. */
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prvSetInterruptGate( ( uint8_t ) portAPIC_SPURIOUS_INT_VECTOR, vPortAPICSpuriousHandler, portIDT_FLAGS );
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/* Enable the APIC, mapping the spurious interrupt at the same time. */
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portAPIC_SPURIOUS_INT = portAPIC_SPURIOUS_INT_VECTOR | portAPIC_ENABLE_BIT;
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/* Set timer error vector. */
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portAPIC_LVT_ERROR = portAPIC_LVT_ERROR_VECTOR;
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/* Set the interrupt frequency. */
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portAPIC_TMRDIV = portAPIC_DIV_16;
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portAPIC_TIMER_INITIAL_COUNT = ( ( configCPU_CLOCK_HZ >> 4UL ) / configTICK_RATE_HZ ) - 1UL;
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}
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/*-----------------------------------------------------------*/
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BaseType_t xPortStartScheduler( void )
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{
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BaseType_t xWord;
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/* Some versions of GCC require the -mno-ms-bitfields command line option
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* for packing to work. */
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configASSERT( sizeof( struct IDTEntry ) == portEXPECTED_IDT_ENTRY_SIZE );
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/* Fill part of the system stack with a known value to help detect stack
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* overflow. A few zeros are left so GDB doesn't get confused unwinding
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* the stack. */
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for( xWord = 0; xWord < configISR_STACK_SIZE - 20; xWord++ )
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{
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ulSystemStack[ xWord ] = portSTACK_WORD;
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}
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/* Initialise Interrupt Descriptor Table (IDT). */
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vPortSetupIDT();
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/* Initialise LAPIC and install system handlers. */
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prvSetupTimerInterrupt();
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/* Make sure the stack used by interrupts is aligned. */
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ulTopOfSystemStack &= ~portBYTE_ALIGNMENT_MASK;
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ulCriticalNesting = 0;
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/* Enable LAPIC Counter.*/
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portAPIC_LVT_TIMER = portAPIC_TIMER_PERIODIC | portAPIC_TIMER_INT_VECTOR;
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/* Sometimes needed. */
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portAPIC_TMRDIV = portAPIC_DIV_16;
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/* Should not return from the following function as the scheduler will then
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* be executing the tasks. */
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vPortStartFirstTask();
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return 0;
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}
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/*-----------------------------------------------------------*/
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void vPortEndScheduler( void )
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{
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/* Not implemented in ports where there is nothing to return to.
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* Artificially force an assert. */
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configASSERT( ulCriticalNesting == 1000UL );
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}
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/*-----------------------------------------------------------*/
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void vPortEnterCritical( void )
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{
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if( ulCriticalNesting == 0 )
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{
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#if ( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
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{
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__asm volatile ( "cli" );
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}
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#else
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{
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portAPIC_TASK_PRIORITY = portMAX_API_CALL_PRIORITY;
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configASSERT( portAPIC_TASK_PRIORITY == portMAX_API_CALL_PRIORITY );
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}
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#endif
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}
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/* Now that interrupts are disabled, ulCriticalNesting can be accessed
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* directly. Increment ulCriticalNesting to keep a count of how many times
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* portENTER_CRITICAL() has been called. */
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ulCriticalNesting++;
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}
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/*-----------------------------------------------------------*/
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void vPortExitCritical( void )
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{
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if( ulCriticalNesting > portNO_CRITICAL_NESTING )
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{
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/* Decrement the nesting count as the critical section is being
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* exited. */
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ulCriticalNesting--;
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/* If the nesting level has reached zero then all interrupt
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* priorities must be re-enabled. */
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if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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{
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/* Critical nesting has reached zero so all interrupt priorities
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* should be unmasked. */
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#if ( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
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{
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__asm volatile ( "sti" );
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}
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#else
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{
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portAPIC_TASK_PRIORITY = 0;
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}
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#endif
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/* If a yield was pended from within the critical section then
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* perform the yield now. */
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if( ulPortYieldPending != pdFALSE )
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{
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ulPortYieldPending = pdFALSE;
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__asm volatile ( portYIELD_INTERRUPT );
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}
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}
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}
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}
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/*-----------------------------------------------------------*/
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uint32_t ulPortSetInterruptMask( void )
|
|
{
|
|
volatile uint32_t ulOriginalMask;
|
|
|
|
/* Set mask to max syscall priority. */
|
|
#if ( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
|
|
{
|
|
/* Return whether interrupts were already enabled or not. Pop adjusts
|
|
* the stack first. */
|
|
__asm volatile ( "pushf \t\n"
|
|
"pop %0 \t\n"
|
|
"cli "
|
|
: "=rm" ( ulOriginalMask )::"memory" );
|
|
|
|
ulOriginalMask &= portEFLAGS_IF;
|
|
}
|
|
#else
|
|
{
|
|
/* Return original mask. */
|
|
ulOriginalMask = portAPIC_TASK_PRIORITY;
|
|
portAPIC_TASK_PRIORITY = portMAX_API_CALL_PRIORITY;
|
|
configASSERT( portAPIC_TASK_PRIORITY == portMAX_API_CALL_PRIORITY );
|
|
}
|
|
#endif /* if ( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY ) */
|
|
|
|
return ulOriginalMask;
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortClearInterruptMask( uint32_t ulNewMaskValue )
|
|
{
|
|
#if ( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
|
|
{
|
|
if( ulNewMaskValue != pdFALSE )
|
|
{
|
|
__asm volatile ( "sti" );
|
|
}
|
|
}
|
|
#else
|
|
{
|
|
portAPIC_TASK_PRIORITY = ulNewMaskValue;
|
|
configASSERT( portAPIC_TASK_PRIORITY == ulNewMaskValue );
|
|
}
|
|
#endif /* if ( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY ) */
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configSUPPORT_FPU == 1 )
|
|
|
|
void vPortTaskUsesFPU( void )
|
|
{
|
|
/* A task is registering the fact that it needs an FPU context. Allocate a
|
|
* buffer into which the context can be saved. */
|
|
pucPortTaskFPUContextBuffer = ( uint8_t * ) pvPortMalloc( portFPU_CONTEXT_SIZE_BYTES );
|
|
configASSERT( pucPortTaskFPUContextBuffer );
|
|
|
|
/* Initialise the floating point registers. */
|
|
__asm volatile ( "fninit" );
|
|
}
|
|
|
|
#endif /* configSUPPORT_FPU */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortAPICErrorHandler( void )
|
|
{
|
|
/* Variable to hold the APIC error status for viewing in the debugger. */
|
|
volatile uint32_t ulErrorStatus = 0;
|
|
|
|
portAPIC_ERROR_STATUS = 0;
|
|
ulErrorStatus = portAPIC_ERROR_STATUS;
|
|
( void ) ulErrorStatus;
|
|
|
|
/* Force an assert. */
|
|
configASSERT( ulCriticalNesting == ~0UL );
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
|
|
|
|
void vPortCentralInterruptHandler( uint32_t ulVector )
|
|
{
|
|
if( ulVector < portNUM_VECTORS )
|
|
{
|
|
if( xInterruptHandlerTable[ ulVector ] != NULL )
|
|
{
|
|
( xInterruptHandlerTable[ ulVector ] )();
|
|
}
|
|
}
|
|
|
|
/* Check for a system stack overflow. */
|
|
configASSERT( ulSystemStack[ 10 ] == portSTACK_WORD );
|
|
configASSERT( ulSystemStack[ 12 ] == portSTACK_WORD );
|
|
configASSERT( ulSystemStack[ 14 ] == portSTACK_WORD );
|
|
}
|
|
|
|
#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
|
|
|
|
BaseType_t xPortRegisterCInterruptHandler( ISR_Handler_t pxHandler,
|
|
uint32_t ulVectorNumber )
|
|
{
|
|
BaseType_t xReturn;
|
|
|
|
xReturn = prvCheckValidityOfVectorNumber( ulVectorNumber );
|
|
|
|
if( xReturn != pdFAIL )
|
|
{
|
|
/* Save the handler passed in by the application in the vector number
|
|
* passed in. The addresses are then called from the central interrupt
|
|
* handler. */
|
|
xInterruptHandlerTable[ ulVectorNumber ] = pxHandler;
|
|
}
|
|
|
|
return xReturn;
|
|
}
|
|
|
|
#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xPortInstallInterruptHandler( ISR_Handler_t pxHandler,
|
|
uint32_t ulVectorNumber )
|
|
{
|
|
BaseType_t xReturn;
|
|
|
|
xReturn = prvCheckValidityOfVectorNumber( ulVectorNumber );
|
|
|
|
if( xReturn != pdFAIL )
|
|
{
|
|
taskENTER_CRITICAL();
|
|
{
|
|
/* Update the IDT to include the application defined handler. */
|
|
prvSetInterruptGate( ( uint8_t ) ulVectorNumber, ( ISR_Handler_t ) pxHandler, portIDT_FLAGS );
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
}
|
|
|
|
return xReturn;
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static BaseType_t prvCheckValidityOfVectorNumber( uint32_t ulVectorNumber )
|
|
{
|
|
BaseType_t xReturn;
|
|
|
|
/* Check validity of vector number. */
|
|
if( ulVectorNumber >= portNUM_VECTORS )
|
|
{
|
|
/* Too high. */
|
|
xReturn = pdFAIL;
|
|
}
|
|
else if( ulVectorNumber < portAPIC_MIN_ALLOWABLE_VECTOR )
|
|
{
|
|
/* Too low. */
|
|
xReturn = pdFAIL;
|
|
}
|
|
else if( ulVectorNumber == portAPIC_TIMER_INT_VECTOR )
|
|
{
|
|
/* In use by FreeRTOS. */
|
|
xReturn = pdFAIL;
|
|
}
|
|
else if( ulVectorNumber == portAPIC_YIELD_INT_VECTOR )
|
|
{
|
|
/* In use by FreeRTOS. */
|
|
xReturn = pdFAIL;
|
|
}
|
|
else if( ulVectorNumber == portAPIC_LVT_ERROR_VECTOR )
|
|
{
|
|
/* In use by FreeRTOS. */
|
|
xReturn = pdFAIL;
|
|
}
|
|
else if( ulVectorNumber == portAPIC_SPURIOUS_INT_VECTOR )
|
|
{
|
|
/* In use by FreeRTOS. */
|
|
xReturn = pdFAIL;
|
|
}
|
|
#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
|
|
else if( xInterruptHandlerTable[ ulVectorNumber ] != NULL )
|
|
{
|
|
/* Already in use by the application. */
|
|
xReturn = pdFAIL;
|
|
}
|
|
#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
|
|
else
|
|
{
|
|
xReturn = pdPASS;
|
|
}
|
|
|
|
return xReturn;
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vGenerateYieldInterrupt( void )
|
|
{
|
|
__asm volatile ( portYIELD_INTERRUPT );
|
|
}
|