mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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458 lines
18 KiB
C
458 lines
18 KiB
C
/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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/*-----------------------------------------------------------
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* Implementation of functions defined in portable.h for the MicroBlaze port.
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*----------------------------------------------------------*/
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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/* Standard includes. */
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#include <string.h>
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/* Hardware includes. */
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#include <xintc_i.h>
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#include <xil_exception.h>
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#include <microblaze_exceptions_g.h>
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/* Tasks are started with a critical section nesting of 0 - however, prior to
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* the scheduler being commenced interrupts should not be enabled, so the critical
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* nesting variable is initialised to a non-zero value. */
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#define portINITIAL_NESTING_VALUE ( 0xff )
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/* The bit within the MSR register that enabled/disables interrupts and
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* exceptions respectively. */
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#define portMSR_IE ( 0x02U )
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#define portMSR_EE ( 0x100U )
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/* If the floating point unit is included in the MicroBlaze build, then the
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* FSR register is saved as part of the task context. portINITIAL_FSR is the value
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* given to the FSR register when the initial context is set up for a task being
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* created. */
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#define portINITIAL_FSR ( 0U )
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/*-----------------------------------------------------------*/
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/*
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* Initialise the interrupt controller instance.
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*/
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static int32_t prvInitialiseInterruptController( void );
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/* Ensure the interrupt controller instance variable is initialised before it is
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* used, and that the initialisation only happens once.
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*/
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static int32_t prvEnsureInterruptControllerIsInitialised( void );
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/*-----------------------------------------------------------*/
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/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task
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* maintains its own count, so this variable is saved as part of the task
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* context. */
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volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
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/* This port uses a separate stack for interrupts. This prevents the stack of
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* every task needing to be large enough to hold an entire interrupt stack on top
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* of the task stack. */
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uint32_t * pulISRStack;
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/* If an interrupt requests a context switch, then ulTaskSwitchRequested will
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* get set to 1. ulTaskSwitchRequested is inspected just before the main interrupt
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* handler exits. If, at that time, ulTaskSwitchRequested is set to 1, the kernel
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* will call vTaskSwitchContext() to ensure the task that runs immediately after
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* the interrupt exists is the highest priority task that is able to run. This is
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* an unusual mechanism, but is used for this port because a single interrupt can
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* cause the servicing of multiple peripherals - and it is inefficient to call
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* vTaskSwitchContext() multiple times as each peripheral is serviced. */
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volatile uint32_t ulTaskSwitchRequested = 0UL;
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/* The instance of the interrupt controller used by this port. This is required
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* by the Xilinx library API functions. */
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static XIntc xInterruptControllerInstance;
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/*-----------------------------------------------------------*/
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/*
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* Initialise the stack of a task to look exactly as if a call to
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* portSAVE_CONTEXT had been made.
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*
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* See the portable.h header file.
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*/
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StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
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TaskFunction_t pxCode,
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void * pvParameters )
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{
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extern void * _SDA2_BASE_;
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extern void * _SDA_BASE_;
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const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
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const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
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/* Place a few bytes of known values on the bottom of the stack.
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* This is essential for the Microblaze port and these lines must
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* not be omitted. */
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*pxTopOfStack = ( StackType_t ) 0x00000000;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x00000000;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x00000000;
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pxTopOfStack--;
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#if ( XPAR_MICROBLAZE_USE_FPU != 0 )
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/* The FSR value placed in the initial task context is just 0. */
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*pxTopOfStack = portINITIAL_FSR;
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pxTopOfStack--;
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#endif
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/* The MSR value placed in the initial task context should have interrupts
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* disabled. Each task will enable interrupts automatically when it enters
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* the running state for the first time. */
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*pxTopOfStack = mfmsr() & ~portMSR_IE;
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#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )
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{
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/* Ensure exceptions are enabled for the task. */
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*pxTopOfStack |= portMSR_EE;
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}
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#endif
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pxTopOfStack--;
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/* First stack an initial value for the critical section nesting. This
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* is initialised to zero. */
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*pxTopOfStack = ( StackType_t ) 0x00;
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/* R0 is always zero. */
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/* R1 is the SP. */
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/* Place an initial value for all the general purpose registers. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) ulR2; /* R2 - read only small data area. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x03; /* R3 - return values and temporaries. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x04; /* R4 - return values and temporaries. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) pvParameters; /* R5 contains the function call parameters. */
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#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x06; /* R6 - other parameters and temporaries. Used as the return address from vPortTaskEntryPoint. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x07; /* R7 - other parameters and temporaries. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x08; /* R8 - other parameters and temporaries. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x09; /* R9 - other parameters and temporaries. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x0a; /* R10 - other parameters and temporaries. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x0b; /* R11 - temporaries. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x0c; /* R12 - temporaries. */
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pxTopOfStack--;
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#else /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
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pxTopOfStack -= 8;
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#endif /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
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*pxTopOfStack = ( StackType_t ) ulR13; /* R13 - read/write small data area. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) pxCode; /* R14 - return address for interrupt. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) NULL; /* R15 - return address for subroutine. */
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#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x10; /* R16 - return address for trap (debugger). */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x11; /* R17 - return address for exceptions, if configured. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x12; /* R18 - reserved for assembler and compiler temporaries. */
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pxTopOfStack--;
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#else
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pxTopOfStack -= 4;
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#endif
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*pxTopOfStack = ( StackType_t ) 0x00; /* R19 - must be saved across function calls. Callee-save. Seems to be interpreted as the frame pointer. */
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#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x14; /* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save. Not used by FreeRTOS. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x15; /* R21 - must be saved across function calls. Callee-save. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x16; /* R22 - must be saved across function calls. Callee-save. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x17; /* R23 - must be saved across function calls. Callee-save. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x18; /* R24 - must be saved across function calls. Callee-save. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x19; /* R25 - must be saved across function calls. Callee-save. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x1a; /* R26 - must be saved across function calls. Callee-save. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x1b; /* R27 - must be saved across function calls. Callee-save. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x1c; /* R28 - must be saved across function calls. Callee-save. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x1d; /* R29 - must be saved across function calls. Callee-save. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x1e; /* R30 - must be saved across function calls. Callee-save. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x1f; /* R31 - must be saved across function calls. Callee-save. */
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pxTopOfStack--;
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#else /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
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pxTopOfStack -= 13;
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#endif /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
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/* Return a pointer to the top of the stack that has been generated so this
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* can be stored in the task control block for the task. */
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return pxTopOfStack;
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}
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/*-----------------------------------------------------------*/
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BaseType_t xPortStartScheduler( void )
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{
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extern void( vPortStartFirstTask )( void );
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extern uint32_t _stack[];
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/* Setup the hardware to generate the tick. Interrupts are disabled when
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* this function is called.
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*
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* This port uses an application defined callback function to install the tick
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* interrupt handler because the kernel will run on lots of different
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* MicroBlaze and FPGA configurations - not all of which will have the same
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* timer peripherals defined or available. An example definition of
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* vApplicationSetupTimerInterrupt() is provided in the official demo
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* application that accompanies this port. */
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vApplicationSetupTimerInterrupt();
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/* Reuse the stack from main() as the stack for the interrupts/exceptions. */
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pulISRStack = ( uint32_t * ) _stack;
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/* Ensure there is enough space for the functions called from the interrupt
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* service routines to write back into the stack frame of the caller. */
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pulISRStack -= 2;
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/* Restore the context of the first task that is going to run. From here
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* on, the created tasks will be executing. */
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vPortStartFirstTask();
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/* Should not get here as the tasks are now running! */
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return pdFALSE;
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}
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/*-----------------------------------------------------------*/
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void vPortEndScheduler( void )
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{
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/* Not implemented in ports where there is nothing to return to.
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* Artificially force an assert. */
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configASSERT( uxCriticalNesting == 1000UL );
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}
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/*-----------------------------------------------------------*/
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/*
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* Manual context switch called by portYIELD or taskYIELD.
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*/
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void vPortYield( void )
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{
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extern void VPortYieldASM( void );
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/* Perform the context switch in a critical section to assure it is
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* not interrupted by the tick ISR. It is not a problem to do this as
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* each task maintains its own interrupt status. */
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portENTER_CRITICAL();
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{
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/* Jump directly to the yield function to ensure there is no
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* compiler generated prologue code. */
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asm volatile ( "bralid r14, VPortYieldASM \n\t" \
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"or r0, r0, r0 \n\t" );
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}
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portEXIT_CRITICAL();
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}
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/*-----------------------------------------------------------*/
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void vPortEnableInterrupt( uint8_t ucInterruptID )
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{
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int32_t lReturn;
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/* An API function is provided to enable an interrupt in the interrupt
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* controller because the interrupt controller instance variable is private
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* to this file. */
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lReturn = prvEnsureInterruptControllerIsInitialised();
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if( lReturn == pdPASS )
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{
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XIntc_Enable( &xInterruptControllerInstance, ucInterruptID );
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}
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configASSERT( lReturn );
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}
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/*-----------------------------------------------------------*/
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void vPortDisableInterrupt( uint8_t ucInterruptID )
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{
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int32_t lReturn;
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/* An API function is provided to disable an interrupt in the interrupt
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* controller because the interrupt controller instance variable is private
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* to this file. */
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lReturn = prvEnsureInterruptControllerIsInitialised();
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if( lReturn == pdPASS )
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{
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XIntc_Disable( &xInterruptControllerInstance, ucInterruptID );
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}
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configASSERT( lReturn );
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}
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/*-----------------------------------------------------------*/
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BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID,
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XInterruptHandler pxHandler,
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void * pvCallBackRef )
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{
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int32_t lReturn;
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/* An API function is provided to install an interrupt handler because the
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* interrupt controller instance variable is private to this file. */
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lReturn = prvEnsureInterruptControllerIsInitialised();
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if( lReturn == pdPASS )
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{
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lReturn = XIntc_Connect( &xInterruptControllerInstance, ucInterruptID, pxHandler, pvCallBackRef );
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}
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if( lReturn == XST_SUCCESS )
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{
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lReturn = pdPASS;
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}
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configASSERT( lReturn == pdPASS );
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return lReturn;
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}
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/*-----------------------------------------------------------*/
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static int32_t prvEnsureInterruptControllerIsInitialised( void )
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{
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static int32_t lInterruptControllerInitialised = pdFALSE;
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int32_t lReturn;
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/* Ensure the interrupt controller instance variable is initialised before
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* it is used, and that the initialisation only happens once. */
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if( lInterruptControllerInitialised != pdTRUE )
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{
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lReturn = prvInitialiseInterruptController();
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if( lReturn == pdPASS )
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{
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lInterruptControllerInitialised = pdTRUE;
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}
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}
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else
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{
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lReturn = pdPASS;
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}
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return lReturn;
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}
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/*-----------------------------------------------------------*/
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/*
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* Handler for the timer interrupt. This is the handler that the application
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* defined callback function vApplicationSetupTimerInterrupt() should install.
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*/
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void vPortTickISR( void * pvUnused )
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{
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extern void vApplicationClearTimerInterrupt( void );
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/* Ensure the unused parameter does not generate a compiler warning. */
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( void ) pvUnused;
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/* This port uses an application defined callback function to clear the tick
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* interrupt because the kernel will run on lots of different MicroBlaze and
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* FPGA configurations - not all of which will have the same timer peripherals
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* defined or available. An example definition of
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* vApplicationClearTimerInterrupt() is provided in the official demo
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* application that accompanies this port. */
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vApplicationClearTimerInterrupt();
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/* Increment the RTOS tick - this might cause a task to unblock. */
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if( xTaskIncrementTick() != pdFALSE )
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{
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/* Force vTaskSwitchContext() to be called as the interrupt exits. */
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ulTaskSwitchRequested = 1;
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}
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}
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/*-----------------------------------------------------------*/
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static int32_t prvInitialiseInterruptController( void )
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{
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int32_t lStatus;
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lStatus = XIntc_Initialize( &xInterruptControllerInstance, configINTERRUPT_CONTROLLER_TO_USE );
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if( lStatus == XST_SUCCESS )
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{
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/* Initialise the exception table. */
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Xil_ExceptionInit();
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/* Service all pending interrupts each time the handler is entered. */
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XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION );
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/* Install exception handlers if the MicroBlaze is configured to handle
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* exceptions, and the application defined constant
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* configINSTALL_EXCEPTION_HANDLERS is set to 1. */
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#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
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{
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vPortExceptionsInstallHandlers();
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}
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#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
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/* Start the interrupt controller. Interrupts are enabled when the
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* scheduler starts. */
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lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE );
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if( lStatus == XST_SUCCESS )
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{
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lStatus = pdPASS;
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}
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else
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{
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lStatus = pdFAIL;
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}
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}
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configASSERT( lStatus == pdPASS );
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return lStatus;
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}
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/*-----------------------------------------------------------*/
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