mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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c5bec0e4b2
GNU as makes unrecognized sections loadable and writable by default, but LLVM's assembler requires specifying flags explicitly. Without them, the linker generates "has non-ABS relocation" errors when trying to link the resulting object files.
499 lines
18 KiB
ArmAsm
499 lines
18 KiB
ArmAsm
/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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.arm
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.syntax unified
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.section privileged_functions, "ax"
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#define FREERTOS_ASSEMBLY
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#include "portmacro_asm.h"
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#include "mpu_syscall_numbers.h"
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#undef FREERTOS_ASSEMBLY
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/* External FreeRTOS-Kernel variables. */
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.extern pxCurrentTCB
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.extern uxSystemCallImplementations
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.extern ulPortInterruptNesting
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.extern ulPortYieldRequired
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/* External Llnker script variables. */
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.extern __syscalls_flash_start__
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.extern __syscalls_flash_end__
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/* External FreeRTOS-Kernel functions. */
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.extern vTaskSwitchContext
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.extern vApplicationIRQHandler
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/* ----------------------------------------------------------------------------------- */
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/* Save the context of a FreeRTOS Task. */
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.macro portSAVE_CONTEXT
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DSB
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ISB
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/* Push R0 and LR to the stack for current mode. */
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PUSH { R0, LR }
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LDR LR, =pxCurrentTCB /* LR = &( pxCurrentTCB ). */
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LDR LR, [LR] /* LR = pxCurrentTCB. */
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LDR LR, [LR] /* LR = pxTopOfStack i.e. the address where to store the task context. */
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LDR R0, =ulCriticalNesting /* R0 = &( ulCriticalNesting ). */
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LDR R0, [R0] /* R0 = ulCriticalNesting. */
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STM LR!, { R0 } /* Store ulCriticalNesting. ! increments LR after storing. */
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#if ( portENABLE_FPU == 1 )
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VMRS R0, FPSCR /* R0 = FPSCR. */
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STM LR!, { R0 } /* Store FPSCR. */
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VSTM LR!, { D0-D15 } /* Store D0-D15. */
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#endif /* ( portENABLE_FPU == 1 ) */
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POP { R0 } /* Restore R0 to pre-exception value. */
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/* STM (user registers) - In a PL1 mode other than System mode, STM (user
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* registers) instruction stores multiple User mode registers to
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* consecutive memory locations using an address from a base register. The
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* processor reads the base register value normally, using the current mode
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* to determine the correct Banked version of the register. This instruction
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* cannot writeback to the base register.
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*
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* The following can be derived from the above description:
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* - The macro portSAVE_CONTEXT MUST be called from a PL1 mode other than
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* the System mode.
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* - Base register LR of the current mode will be used which contains the
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* location to store the context.
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* - It will store R0-R14 of User mode i.e. pre-exception SP(R13) and LR(R14)
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* will be stored. */
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STM LR, { R0-R14 }^
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ADD LR, LR, #60 /* R0-R14 - Total 155 register, each 4 byte wide. */
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POP { R0 } /* Pre-exception PC is in R0. */
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MRS R1, SPSR /* R1 = Pre-exception CPSR. */
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STM LR!, { R0-R1 } /* Store pre-exception PC and CPSR. */
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.endm
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/* ----------------------------------------------------------------------------------- */
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/* Restore the context of a FreeRTOS Task. */
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.macro portRESTORE_CONTEXT
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/* Load the pointer to the current task's Task Control Block (TCB). */
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LDR LR, =pxCurrentTCB /* LR = &( pxCurrentTCB ). */
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LDR LR, [LR] /* LR = pxCurrentTCB. */
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ADD R1, LR, #0x4 /* R1 now points to the xMPUSettings in TCB. */
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LDR LR, [LR] /* LR = pxTopOfStack i.e. the address where to restore the task context from. */
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/* When creating a loop label in a macro it has to be a numeric label.
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* for( R5 = portFIRST_CONFIGURABLE_REGION ; R5 <= portNUM_CONFIGURABLE_REGIONS ; R5++ ) */
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MOV R5, #portFIRST_CONFIGURABLE_REGION
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123:
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LDMIA R1!, { R2-R4 } /* R2 = ulRegionSize, R3 = ulRegionAttribute, R4 = ulRegionBaseAddress. */
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MCR p15, #0, R5, c6, c2, #0 /* MPU Region Number Register. */
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MCR p15, #0, R4, c6, c1, #0 /* MPU Region Base Address Register. */
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MCR p15, #0, R3, c6, c1, #4 /* MPU Region Access Control Register. */
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MCR p15, #0, R2, c6, c1, #2 /* MPU Region Size and Enable Register. */
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ADD R5, R5, #1
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CMP R5, #portNUM_CONFIGURABLE_REGIONS
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BLE 123b
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LDR R1, =ulCriticalNesting /* R1 = &( ulCriticalNesting ). */
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LDM LR!, { R2 } /* R2 = Stored ulCriticalNesting. */
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STR R2, [R1] /* Restore ulCriticalNesting. */
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#if ( portENABLE_FPU == 1 )
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LDM LR!, { R1 } /* R1 = Stored FPSCR. */
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VMSR FPSCR, R1 /* Restore FPSCR. */
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VLDM LR!, { D0-D15 } /* Restore D0-D15. */
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#endif /* portENABLE_FPU*/
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/* LDM (User registers) - In a PL1 mode other than System mode, LDM (User
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* registers) loads multiple User mode registers from consecutive memory
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* locations using an address from a base register. The registers loaded
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* cannot include the PC. The processor reads the base register value
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* normally, using the current mode to determine the correct Banked version
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* of the register. This instruction cannot writeback to the base register.
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*
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* The following can be derived from the above description:
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* - The macro portRESTORE_CONTEXT MUST be called from a PL1 mode other than
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* the System mode.
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* - Base register LR of the current mode will be used which contains the
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* location to restore the context from.
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* - It will restore R0-R14 of User mode i.e. SP(R13) and LR(R14) of User
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* mode will be restored.
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*/
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LDM LR, { R0-R14 }^
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ADD LR, LR, #60 /* R0-R14 - Total 155 register, each 4 byte wide. */
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RFE LR /* Restore PC and CPSR from the context. */
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.endm
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/* ----------------------------------------------------------------------------------- */
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/*
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* void vPortStartFirstTask( void );
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*/
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.align 4
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.global vPortStartFirstTask
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.type vPortStartFirstTask, %function
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vPortStartFirstTask:
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/* This function is called from System Mode to start the FreeRTOS-Kernel.
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* As described in the portRESTORE_CONTEXT macro, portRESTORE_CONTEXT cannot
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* be called from the System mode. We, therefore, switch to the Supervisor
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* mode before calling portRESTORE_CONTEXT. */
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CPS #SVC_MODE
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portRESTORE_CONTEXT
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/* ----------------------------------------------------------------------------------- */
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.align 4
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.global FreeRTOS_SVC_Handler
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.type FreeRTOS_SVC_Handler, %function
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FreeRTOS_SVC_Handler:
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PUSH { R11-R12 }
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/* ------------------------- Caller Flash Location Check ------------------------- */
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LDR R11, =__syscalls_flash_start__
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LDR R12, =__syscalls_flash_end__
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CMP LR, R11 /* If SVC instruction address is less than __syscalls_flash_start__, exit. */
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BLT svcHandlerExit
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CMP LR, R12 /* If SVC instruction address is greater than __syscalls_flash_end__, exit. */
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BGT svcHandlerExit
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/* ---------------------------- Get Caller SVC Number ---------------------------- */
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MRS R11, SPSR /* LR = CPSR at the time of SVC. */
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TST R11, #0x20 /* Check Thumb bit (5) in CPSR. */
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LDRHNE R11, [LR, #-0x2] /* If Thumb, load halfword. */
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BICNE R11, R11, #0xFF00 /* And extract immidiate field (i.e. SVC number). */
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LDREQ R11, [LR, #-0x4] /* If ARM, load word. */
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BICEQ R11, R11, #0xFF000000 /* And extract immidiate field (i.e. SVC number). */
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/* --------------------------------- SVC Routing --------------------------------- */
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/* If SVC Number < #NUM_SYSTEM_CALLS, go to svcSystemCallEnter. */
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CMP R11, #NUM_SYSTEM_CALLS
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BLT svcSystemCallEnter
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/* If SVC Number == #portSVC_SYSTEM_CALL_EXIT, go to svcSystemCallExit. */
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CMP R11, #portSVC_SYSTEM_CALL_EXIT
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BEQ svcSystemCallExit
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/* If SVC Number == #portSVC_YIELD, go to svcPortYield. */
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CMP R11, #portSVC_YIELD
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BEQ svcPortYield
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svcHandlerExit:
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POP { R11-R12 }
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MOVS PC, LR /* Copies the SPSR into the CPSR, performing the mode swap. */
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svcPortYield:
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POP { R11-R12 }
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portSAVE_CONTEXT
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BL vTaskSwitchContext
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portRESTORE_CONTEXT
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svcSystemCallExit:
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LDR R11, =pxCurrentTCB /* R11 = &( pxCurrentTCB ). */
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LDR R11, [R11] /* R11 = pxCurrentTCB. */
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ADD R11, R11, #portSYSTEM_CALL_INFO_OFFSET /* R11 now points to xSystemCallStackInfo in TCB. */
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/* Restore the user mode SP and LR. */
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LDM R11, { R13-R14 }^
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AND R12, R12, #0x0 /* R12 = 0. */
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STR R12, [R11] /* xSystemCallStackInfo.pulTaskStackPointer = NULL. */
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STR R12, [R11, #0x4] /* xSystemCallStackInfo.pulLinkRegisterAtSystemCallEntry = NULL. */
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LDMDB R11, { R12 } /* R12 = ulTaskFlags. */
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TST R12, #portTASK_IS_PRIVILEGED_FLAG
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/* If the task is privileged, we can exit now. */
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BNE svcHandlerExit
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/* Otherwise, we need to switch back to User mode. */
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MRS R12, SPSR
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BIC R12, R12, #0x0F
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MSR SPSR_cxsf, R12
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B svcHandlerExit
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svcSystemCallEnter:
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LDR R12, =uxSystemCallImplementations /* R12 = uxSystemCallImplementations. */
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/* R12 = uxSystemCallImplementations[ R12 + ( R11 << 2 ) ].
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* R12 now contains the address of the system call impl function. */
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LDR R12, [R12, R11, lsl #2]
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/* If R12 == NULL, exit. */
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CMP R12, #0x0
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BEQ svcHandlerExit
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/* It is okay to clobber LR here because we do not need to return to the
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* SVC enter location anymore. LR now contains the address of the system
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* call impl function. */
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MOV LR, R12
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LDR R11, =pxCurrentTCB /* R11 = &( pxCurrentTCB ). */
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LDR R11, [R11] /* R11 = pxCurrentTCB. */
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ADD R11, R11, #portSYSTEM_CALL_INFO_OFFSET /* R11 now points to xSystemCallStackInfo in TCB. */
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/* Store User mode SP and LR in xSystemCallStackInfo.pulTaskStackPointer and
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* xSystemCallStackInfo.pulLinkRegisterAtSystemCallEntry. */
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STM R11, { R13-R14 }^
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ADD R11, R11, 0x8
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/* Load User mode SP an LR with xSystemCallStackInfo.pulSystemCallStackPointer
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* and xSystemCallStackInfo.pulSystemCallExitAddress. */
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LDM R11, { R13-R14 }^
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/* Change to SYS_MODE for the System Call. */
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MRS R12, SPSR
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ORR R12, R12, #SYS_MODE
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MSR SPSR_cxsf, R12
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B svcHandlerExit
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/* ----------------------------------------------------------------------------------- */
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/*
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* void vPortDisableInterrupts( void );
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*/
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.align 4
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.global vPortDisableInterrupts
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.type vPortDisableInterrupts, %function
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vPortDisableInterrupts:
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CPSID I
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BX LR
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/* ----------------------------------------------------------------------------------- */
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/*
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* void vPortEnableInterrupts( void );
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*/
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.align 4
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.global vPortEnableInterrupts
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.type vPortEnableInterrupts, %function
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vPortEnableInterrupts:
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CPSIE I
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BX LR
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/* ----------------------------------------------------------------------------------- */
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/*
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* void vMPUSetRegion( uint32_t ulRegionNumber,
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* uint32_t ulBaseAddress,
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* uint32_t ulRegionSize,
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* uint32_t ulRegionPermissions );
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*
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* According to the Procedure Call Standard for the ARM Architecture (AAPCS),
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* paramters are passed in the following registers:
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* R0 = ulRegionNumber.
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* R1 = ulBaseAddress.
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* R2 = ulRegionSize.
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* R3 = ulRegionPermissions.
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*/
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.align 4
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.global vMPUSetRegion
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.type vMPUSetRegion, %function
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vMPUSetRegion:
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AND R0, R0, #0x0F /* R0 = R0 & 0x0F. Max possible region number is 15. */
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MCR p15, #0, R0, c6, c2, #0 /* MPU Region Number Register. */
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MCR p15, #0, R1, c6, c1, #0 /* MPU Region Base Address Register. */
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MCR p15, #0, R3, c6, c1, #4 /* MPU Region Access Control Register. */
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MCR p15, #0, R2, c6, c1, #2 /* MPU Region Size and Enable Register. */
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BX LR
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/* ----------------------------------------------------------------------------------- */
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/*
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* void vMPUEnable( void );
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*/
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.align 4
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.global vMPUEnable
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.type vMPUEnable, %function
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vMPUEnable:
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PUSH { R0 }
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MRC p15, #0, R0, c1, c0, #0 /* R0 = System Control Register (SCTLR). */
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ORR R0, R0, #0x1 /* R0 = R0 | 0x1. Set the M bit in SCTLR. */
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DSB
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MCR p15, #0, R0, c1, c0, #0 /* SCTLR = R0. */
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ISB
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POP { R0 }
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BX LR
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/* ----------------------------------------------------------------------------------- */
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/*
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* void vMPUDisable( void );
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*/
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.align 4
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.global vMPUDisable
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.type vMPUDisable, %function
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vMPUDisable:
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PUSH { R0 }
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MRC p15, #0, R0, c1, c0, #0 /* R0 = System Control Register (SCTLR). */
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BIC R0, R0, #1 /* R0 = R0 & ~0x1. Clear the M bit in SCTLR. */
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/* Wait for all pending data accesses to complete. */
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DSB
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MCR p15, #0, R0, c1, c0, #0 /* SCTLR = R0. */
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/* Flush the pipeline and prefetch buffer(s) in the processor to ensure that
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* all following instructions are fetched from cache or memory. */
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ISB
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POP { R0 }
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BX LR
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/* ----------------------------------------------------------------------------------- */
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/*
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* void vMPUEnableBackgroundRegion( void );
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*/
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.align 4
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.global vMPUEnableBackgroundRegion
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.type vMPUEnableBackgroundRegion, %function
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vMPUEnableBackgroundRegion:
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PUSH { R0 }
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MRC p15, #0, R0, c1, c0, #0 /* R0 = System Control Register (SCTLR). */
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ORR R0, R0, #0x20000 /* R0 = R0 | 0x20000. Set the BR bit in SCTLR. */
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MCR p15, #0, R0, c1, c0, #0 /* SCTLR = R0. */
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POP { R0 }
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BX LR
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/* ----------------------------------------------------------------------------------- */
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/*
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* void vMPUDisableBackgroundRegion( void );
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*/
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.align 4
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.global vMPUDisableBackgroundRegion
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.type vMPUDisableBackgroundRegion, %function
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vMPUDisableBackgroundRegion:
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PUSH { R0 }
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MRC p15, 0, R0, c1, c0, 0 /* R0 = System Control Register (SCTLR). */
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BIC R0, R0, #0x20000 /* R0 = R0 & ~0x20000. Clear the BR bit in SCTLR. */
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MCR p15, 0, R0, c1, c0, 0 /* SCTLR = R0. */
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POP { R0 }
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BX LR
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/* ----------------------------------------------------------------------------------- */
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.align 4
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.global FreeRTOS_IRQ_Handler
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.type FreeRTOS_IRQ_Handler, %function
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FreeRTOS_IRQ_Handler:
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SUB LR, LR, #4 /* Return to the interrupted instruction. */
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SRSDB SP!, #IRQ_MODE /* Save return state (i.e. SPSR_irq and LR_irq) to the IRQ stack. */
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/* Change to supervisor mode to allow reentry. It is necessary to ensure
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* that a BL instruction within the interrupt handler code does not
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* overwrite LR_irq. */
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CPS #SVC_MODE
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PUSH { R0-R3, R12 } /* Push AAPCS callee saved registers. */
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/* Update interrupt nesting count. */
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LDR R0, =ulPortInterruptNesting /* R0 = &( ulPortInterruptNesting ). */
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LDR R1, [R0] /* R1 = ulPortInterruptNesting. */
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ADD R2, R1, #1 /* R2 = R1 + 1. */
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STR R2, [R0] /* Store the updated nesting count. */
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/* Call the application provided IRQ handler. */
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PUSH { R0-R3, LR }
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BL vApplicationIRQHandler
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POP { R0-R3, LR }
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/* Disable IRQs incase vApplicationIRQHandler enabled them for re-entry. */
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CPSID I
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DSB
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ISB
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/* Restore the old interrupt nesting count. R0 holds the address of
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* ulPortInterruptNesting and R1 holds original value of
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* ulPortInterruptNesting. */
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STR R1, [R0]
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/* Context switch is only performed when interrupt nesting count is 0. */
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CMP R1, #0
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BNE exit_without_switch
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/* Check ulPortInterruptNesting to see if the interrupt requested a context
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* switch. */
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LDR R1, =ulPortYieldRequired /* R1 = &( ulPortYieldRequired ). */
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LDR R0, [R1] /* R0 = ulPortYieldRequired. */
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/* If ulPortYieldRequired != 0, goto switch_before_exit. */
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CMP R0, #0
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BNE switch_before_exit
|
|
|
|
exit_without_switch:
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|
POP { R0-R3, R12 } /* Restore AAPCS callee saved registers. */
|
|
CPS #IRQ_MODE
|
|
RFE SP!
|
|
|
|
switch_before_exit:
|
|
/* A context switch is to be performed. Clear ulPortYieldRequired. R1 holds
|
|
* the address of ulPortYieldRequired. */
|
|
MOV R0, #0
|
|
STR R0, [R1]
|
|
|
|
/* Restore AAPCS callee saved registers, SPSR_irq and LR_irq before saving
|
|
* the task context. */
|
|
POP { R0-R3, R12 }
|
|
CPS #IRQ_MODE
|
|
/* The contents of the IRQ stack at this point is the following:
|
|
* +----------+
|
|
* SP+4 | SPSR_irq |
|
|
* +----------+
|
|
* SP | LR_irq |
|
|
* +----------+
|
|
*/
|
|
LDMIB SP!, { LR }
|
|
MSR SPSR_cxsf, LR
|
|
LDMDB SP, { LR }
|
|
ADD SP, SP, 0x4
|
|
portSAVE_CONTEXT
|
|
|
|
/* Call the function that selects the new task to execute. */
|
|
BLX vTaskSwitchContext
|
|
|
|
/* Restore the context of, and branch to, the task selected to execute
|
|
* next. */
|
|
portRESTORE_CONTEXT
|
|
|
|
/* ----------------------------------------------------------------------------------- */
|
|
|
|
.end
|