mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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de276eb023
* Fix spelling --------- Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com>
280 lines
13 KiB
C
280 lines
13 KiB
C
/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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#ifndef PORTMACRO_ASM_H
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#define PORTMACRO_ASM_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "FreeRTOSConfig.h"
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#ifndef configTOTAL_MPU_REGIONS
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#error "Set configTOTAL_MPU_REGIONS to the number of MPU regions in FreeRTOSConfig.h"
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#elif( configTOTAL_MPU_REGIONS == 12 )
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#define portMPU_TOTAL_REGIONS ( 12UL )
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#elif( configTOTAL_MPU_REGIONS == 16 )
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#define portMPU_TOTAL_REGIONS ( 16UL )
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#else
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#error "Set configTOTAL_MPU_REGIONS to the number of MPU regions in FreeRTOSConfig.h"
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#endif /* configTOTAL_MPU_REGIONS */
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/*
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* The application write can disable Floating Point Unit (FPU) support by
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* setting configENABLE_FPU to 0. Floating point context stored in TCB
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* comprises of 32 floating point registers (D0-D31) and FPSCR register.
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* Disabling FPU, therefore, reduces the per-task RAM usage by
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* ( 32 + 1 ) * 4 = 132 bytes per task.
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*
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* BE CAREFUL DISABLING THIS: Certain standard library APIs try to optimize
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* themselves by using the floating point registers. If the FPU support is
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* disabled, the use of such APIs may result in memory corruption.
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*/
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#ifndef configENABLE_FPU
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#define configENABLE_FPU 1
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#endif /* configENABLE_FPU */
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#define portENABLE_FPU configENABLE_FPU
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/* On the ArmV7-R Architecture the Operating mode of the Processor is set
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* using the Current Program Status Register (CPSR) Mode bits, [4:0]. The only
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* unprivileged mode is User Mode.
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*
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* Additional information about the Processor Modes can be found here:
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* https://developer.arm.com/documentation/ddi0406/cb/System-Level-Architecture/The-System-Level-Programmers--Model/ARM-processor-modes-and-ARM-core-registers/ARM-processor-modes?lang=en
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*
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*/
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/**
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* @brief CPSR bits for various processor modes.
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*
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* @ingroup Port Privilege
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*/
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#define USER_MODE 0x10U
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#define FIQ_MODE 0x11U
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#define IRQ_MODE 0x12U
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#define SVC_MODE 0x13U
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#define MON_MODE 0x16U
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#define ABT_MODE 0x17U
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#define HYP_MODE 0x1AU
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#define UND_MODE 0x1BU
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#define SYS_MODE 0x1FU
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/**
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* @brief Flag used to mark that a FreeRTOS Task is privileged.
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*
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* @ingroup Port Privilege
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*/
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#define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
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/**
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* @brief SVC numbers for various scheduler operations.
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*
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* @ingroup Scheduler
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*
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* @note These value must not be used in mpu_syscall_numbers.h.
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*/
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#define portSVC_YIELD 0x0100U
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#define portSVC_SYSTEM_CALL_EXIT 0x0104U
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/**
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* @brief Macros required to manipulate MPU.
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*
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* Further information about MPU can be found in Arm's documentation
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* https://developer.arm.com/documentation/ddi0363/g/System-Control/Register-descriptions/c6--MPU-memory-region-programming-registers
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*
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*/
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/* MPU sub-region disable settings. This information is encoded in the MPU
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* Region Size and Enable Register. */
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#define portMPU_SUBREGION_0_DISABLE ( 0x1UL << 8UL )
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#define portMPU_SUBREGION_1_DISABLE ( 0x1UL << 9UL )
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#define portMPU_SUBREGION_2_DISABLE ( 0x1UL << 10UL )
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#define portMPU_SUBREGION_3_DISABLE ( 0x1UL << 11UL )
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#define portMPU_SUBREGION_4_DISABLE ( 0x1UL << 12UL )
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#define portMPU_SUBREGION_5_DISABLE ( 0x1UL << 13UL )
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#define portMPU_SUBREGION_6_DISABLE ( 0x1UL << 14UL )
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#define portMPU_SUBREGION_7_DISABLE ( 0x1UL << 15UL )
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/* Default MPU regions. */
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#define portFIRST_CONFIGURABLE_REGION ( 0 )
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#define portLAST_CONFIGURABLE_REGION ( portMPU_TOTAL_REGIONS - 5UL )
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#define portSTACK_REGION ( portMPU_TOTAL_REGIONS - 4UL )
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#define portUNPRIVILEGED_FLASH_REGION ( portMPU_TOTAL_REGIONS - 3UL )
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#define portPRIVILEGED_FLASH_REGION ( portMPU_TOTAL_REGIONS - 2UL )
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#define portPRIVILEGED_RAM_REGION ( portMPU_TOTAL_REGIONS - 1UL )
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#define portNUM_CONFIGURABLE_REGIONS \
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( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1UL )
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/* Plus one to make space for the stack region. */
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#define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1UL )
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/* MPU region sizes. This information is encoded in the MPU Region Size and
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* Enable Register. */
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#define portMPU_REGION_SIZE_32B ( 0x04UL << 1UL )
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#define portMPU_REGION_SIZE_64B ( 0x05UL << 1UL )
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#define portMPU_REGION_SIZE_128B ( 0x06UL << 1UL )
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#define portMPU_REGION_SIZE_256B ( 0x07UL << 1UL )
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#define portMPU_REGION_SIZE_512B ( 0x08UL << 1UL )
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#define portMPU_REGION_SIZE_1KB ( 0x09UL << 1UL )
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#define portMPU_REGION_SIZE_2KB ( 0x0AUL << 1UL )
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#define portMPU_REGION_SIZE_4KB ( 0x0BUL << 1UL )
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#define portMPU_REGION_SIZE_8KB ( 0x0CUL << 1UL )
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#define portMPU_REGION_SIZE_16KB ( 0x0DUL << 1UL )
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#define portMPU_REGION_SIZE_32KB ( 0x0EUL << 1UL )
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#define portMPU_REGION_SIZE_64KB ( 0x0FUL << 1UL )
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#define portMPU_REGION_SIZE_128KB ( 0x10UL << 1UL )
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#define portMPU_REGION_SIZE_256KB ( 0x11UL << 1UL )
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#define portMPU_REGION_SIZE_512KB ( 0x12UL << 1UL )
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#define portMPU_REGION_SIZE_1MB ( 0x13UL << 1UL )
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#define portMPU_REGION_SIZE_2MB ( 0x14UL << 1UL )
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#define portMPU_REGION_SIZE_4MB ( 0x15UL << 1UL )
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#define portMPU_REGION_SIZE_8MB ( 0x16UL << 1UL )
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#define portMPU_REGION_SIZE_16MB ( 0x17UL << 1UL )
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#define portMPU_REGION_SIZE_32MB ( 0x18UL << 1UL )
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#define portMPU_REGION_SIZE_64MB ( 0x19UL << 1UL )
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#define portMPU_REGION_SIZE_128MB ( 0x1AUL << 1UL )
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#define portMPU_REGION_SIZE_256MB ( 0x1BUL << 1UL )
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#define portMPU_REGION_SIZE_512MB ( 0x1CUL << 1UL )
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#define portMPU_REGION_SIZE_1GB ( 0x1DUL << 1UL )
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#define portMPU_REGION_SIZE_2GB ( 0x1EUL << 1UL )
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#define portMPU_REGION_SIZE_4GB ( 0x1FUL << 1UL )
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/* MPU memory types. This information is encoded in the TEX, S, C and B bits
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* of the MPU Region Access Control Register. */
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#define portMPU_REGION_STRONGLY_ORDERED_SHAREABLE ( 0x00UL ) /* TEX=000, S=NA, C=0, B=0. */
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#define portMPU_REGION_DEVICE_SHAREABLE ( 0x01UL ) /* TEX=000, S=NA, C=0, B=1. */
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#define portMPU_REGION_NORMAL_OIWTNOWA_NONSHARED ( 0x02UL ) /* TEX=000, S=0, C=1, B=0. */
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#define portMPU_REGION_NORMAL_OIWTNOWA_SHARED ( 0x06UL ) /* TEX=000, S=1, C=1, B=0. */
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#define portMPU_REGION_NORMAL_OIWBNOWA_NONSHARED ( 0x03UL ) /* TEX=000, S=0, C=1, B=1. */
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#define portMPU_REGION_NORMAL_OIWBNOWA_SHARED ( 0x07UL ) /* TEX=000, S=1, C=1, B=1. */
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#define portMPU_REGION_NORMAL_OINC_NONSHARED ( 0x08UL ) /* TEX=001, S=0, C=0, B=0. */
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#define portMPU_REGION_NORMAL_OINC_SHARED ( 0x0CUL ) /* TEX=001, S=1, C=0, B=0. */
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#define portMPU_REGION_NORMAL_OIWBWA_NONSHARED ( 0x0BUL ) /* TEX=001, S=0, C=1, B=1. */
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#define portMPU_REGION_NORMAL_OIWBWA_SHARED ( 0x0FUL ) /* TEX=001, S=1, C=1, B=1. */
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#define portMPU_REGION_DEVICE_NONSHAREABLE ( 0x10UL ) /* TEX=010, S=NA, C=0, B=0. */
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/* MPU access permissions. This information is encoded in the XN and AP bits of
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* the MPU Region Access Control Register. */
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#define portMPU_REGION_AP_BITMASK ( 0x07UL << 8UL )
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#define portMPU_REGION_XN_BITMASK ( 0x01UL << 12UL )
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#define portMPU_REGION_PRIV_NA_USER_NA ( 0x00UL << 8UL )
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#define portMPU_REGION_PRIV_NA_USER_NA_EXEC ( portMPU_REGION_PRIV_NA_USER_NA ) /* Priv: X, Unpriv: X. */
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#define portMPU_REGION_PRIV_NA_USER_NA_NOEXEC ( portMPU_REGION_PRIV_NA_USER_NA | \
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portMPU_REGION_XN_BITMASK ) /* Priv: No Access, Unpriv: No Access. */
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#define portMPU_REGION_PRIV_RW_USER_NA ( 0x01UL << 8UL )
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#define portMPU_REGION_PRIV_RW_USER_NA_EXEC ( portMPU_REGION_PRIV_RW_USER_NA ) /* Priv: RWX, Unpriv: X. */
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#define portMPU_REGION_PRIV_RW_USER_NA_NOEXEC ( portMPU_REGION_PRIV_RW_USER_NA | \
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portMPU_REGION_XN_BITMASK ) /* Priv: RW, Unpriv: No access. */
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#define portMPU_REGION_PRIV_RW_USER_RO ( 0x02UL << 8UL )
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#define portMPU_REGION_PRIV_RW_USER_RO_EXEC ( portMPU_REGION_PRIV_RW_USER_RO ) /* Priv: RWX, Unpriv: RX. */
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#define portMPU_REGION_PRIV_RW_USER_RO_NOEXEC ( portMPU_REGION_PRIV_RW_USER_RO | \
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portMPU_REGION_XN_BITMASK ) /* Priv: RW, Unpriv: R. */
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#define portMPU_REGION_PRIV_RW_USER_RW ( 0x03UL << 8UL )
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#define portMPU_REGION_PRIV_RW_USER_RW_EXEC ( portMPU_REGION_PRIV_RW_USER_RW ) /* Priv: RWX, Unpriv: RWX. */
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#define portMPU_REGION_PRIV_RW_USER_RW_NOEXEC ( portMPU_REGION_PRIV_RW_USER_RW | \
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portMPU_REGION_XN_BITMASK ) /* Priv: RW, Unpriv: RW. */
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#define portMPU_REGION_PRIV_RO_USER_NA ( 0x05UL << 8UL )
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#define portMPU_REGION_PRIV_RO_USER_NA_EXEC ( portMPU_REGION_PRIV_RO_USER_NA ) /* Priv: RX, Unpriv: X. */
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#define portMPU_REGION_PRIV_RO_USER_NA_NOEXEC ( portMPU_REGION_PRIV_RO_USER_NA | \
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portMPU_REGION_XN_BITMASK ) /* Priv: R, Unpriv: No access. */
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#define portMPU_REGION_PRIV_RO_USER_RO ( 0x06UL << 8UL )
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#define portMPU_REGION_PRIV_RO_USER_RO_EXEC ( portMPU_REGION_PRIV_RO_USER_RO ) /* Priv: RX, Unpriv: RX. */
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#define portMPU_REGION_PRIV_RO_USER_RO_NOEXEC ( portMPU_REGION_PRIV_RO_USER_RO | \
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portMPU_REGION_XN_BITMASK ) /* Priv: R, Unpriv: R. */
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/* MPU region management. */
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#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 12UL )
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#define portMPU_REGION_ENABLE ( 0x01UL )
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/**
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* @brief The size (in words) of a task context.
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*
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* An array of this size is allocated in TCB where a task's context is saved
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* when it is switched out.
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*
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* Information about Floating Point Unit (FPU):
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* https://developer.arm.com/documentation/den0042/a/Floating-Point
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*
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* Additional information related to the Cortex R4-F's FPU Implementation:
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* https://developer.arm.com/documentation/ddi0363/e/fpu-programmer-s-model
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*
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* Additional information related to the Cortex R5-F's FPU Implementation:
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* https://developer.arm.com/documentation/ddi0460/d/FPU-Programmers-Model
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*
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* Additional information related to the ArmV7-R CPSR:
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* https://developer.arm.com/documentation/ddi0406/cb/Application-Level-Architecture/Application-Level-Programmers--Model/The-Application-Program-Status-Register--APSR-?lang=en
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*
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* Additional information related to the GPRs:
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* https://developer.arm.com/documentation/ddi0406/cb/System-Level-Architecture/The-System-Level-Programmers--Model/ARM-processor-modes-and-ARM-core-registers/ARM-core-registers?lang=en
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*
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*/
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#if( portENABLE_FPU == 1 )
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/*
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* +-------------------+-------+----------+--------+----------+----------+----------+------+
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* | ulCriticalNesting | FPSCR | S0-S31 | R0-R12 | SP (R13) | LR (R14) | PC (R15) | CPSR |
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* +-------------------+-------+----------+--------+----------+----------+----------+------+
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*
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* <------------------><------><---------><--------><---------><--------><----------><----->
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* 1 1 32 13 1 1 1 1
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*/
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#define CONTEXT_SIZE 51U
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#else
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/*
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* +-------------------+--------+----------+----------+----------+------+
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* | ulCriticalNesting | R0-R12 | SP (R13) | LR (R14) | PC (R15) | CPSR |
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* +-------------------+--------+----------+----------+----------+------+
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*
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* <------------------><--------><---------><--------><----------><----->
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* 1 13 1 1 1 1
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*/
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#define CONTEXT_SIZE 18U
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#endif /* CONTEXT_SIZE */
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/**
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* @brief Offset of xSystemCallStackInfo from the start of a TCB.
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*/
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#define portSYSTEM_CALL_INFO_OFFSET \
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( ( 1U /* pxTopOfStack. */ + \
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( portTOTAL_NUM_REGIONS_IN_TCB * 3U ) + \
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1U /* ulTaskFlags. */ \
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) * 4U )
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#ifdef __cplusplus
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} /* extern C */
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#endif
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#endif /* PORTMACRO_ASM_H */
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