325 lines
10 KiB
C
325 lines
10 KiB
C
/**
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******************************************************************************
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* @file mfxstm32l152_reg.h
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* @author MCD Application Team
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* @brief This file contains all the functions prototypes for the
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* mfxstm32l152_reg.c IO expander driver.
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2018 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef MFXSTM32L152_REG_H
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#define MFXSTM32L152_REG_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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/* Includes ------------------------------------------------------------------*/
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/** @addtogroup BSP
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* @{
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*/
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/** @addtogroup Component
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* @{
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*/
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/** @defgroup MFXSTM32L152
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* @{
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*/
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/** @addtogroup MFXSTM32L152_Exported_Constants
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* @{
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*/
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/**
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* @brief Register address: chip IDs (R)
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*/
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#define MFXSTM32L152_REG_ADR_ID 0x00U
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/**
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* @brief Register address: chip FW_VERSION (R)
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*/
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#define MFXSTM32L152_REG_ADR_FW_VERSION_MSB 0x01U
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#define MFXSTM32L152_REG_ADR_FW_VERSION_LSB 0x00U
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/**
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* @brief Register address: System Control Register (R/W)
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*/
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#define MFXSTM32L152_REG_ADR_SYS_CTRL 0x40U
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/**
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* @brief Register address: Vdd monitoring (R)
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*/
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#define MFXSTM32L152_REG_ADR_VDD_REF_MSB 0x06U
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#define MFXSTM32L152_REG_ADR_VDD_REF_LSB 0x07U
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/**
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* @brief Register address: Error source
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*/
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#define MFXSTM32L152_REG_ADR_ERROR_SRC 0x03U
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/**
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* @brief Register address: Error Message
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*/
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#define MFXSTM32L152_REG_ADR_ERROR_MSG 0x04U
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/**
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* @brief Reg Addr IRQs: to config the pin that informs Main MCU that MFX events appear
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*/
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#define MFXSTM32L152_REG_ADR_MFX_IRQ_OUT 0x41U
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/**
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* @brief Reg Addr IRQs: to select the events which activate the MFXSTM32L152_IRQ_OUT signal
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*/
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#define MFXSTM32L152_REG_ADR_IRQ_SRC_EN 0x42U
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/**
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* @brief Reg Addr IRQs: the Main MCU must read the IRQ_PENDING register to know the interrupt reason
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*/
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#define MFXSTM32L152_REG_ADR_IRQ_PENDING 0x08U
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/**
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* @brief Reg Addr IRQs: the Main MCU must acknowledge it thanks to a writing access to the IRQ_ACK register
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*/
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#define MFXSTM32L152_REG_ADR_IRQ_ACK 0x44U
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/**
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* @brief GPIO: 24 programmable input/output called MFXSTM32L152_GPIO[23:0] are provided
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*/
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/**
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* @brief Reg addr: GPIO DIRECTION (R/W): GPIO pins direction: (0) input, (1) output.
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*/
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#define MFXSTM32L152_REG_ADR_GPIO_DIR1 0x60U /* gpio [0:7] */
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#define MFXSTM32L152_REG_ADR_GPIO_DIR2 0x61U /* gpio [8:15] */
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#define MFXSTM32L152_REG_ADR_GPIO_DIR3 0x62U /* agpio [0:7] */
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/**
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* @brief Reg addr: GPIO TYPE (R/W): If GPIO in output: (0) output push pull, (1) output open drain.
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If GPIO in input: (0) input without pull resistor, (1) input with pull resistor.
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*/
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#define MFXSTM32L152_REG_ADR_GPIO_TYPE1 0x64U /* gpio [0:7] */
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#define MFXSTM32L152_REG_ADR_GPIO_TYPE2 0x65U /* gpio [8:15] */
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#define MFXSTM32L152_REG_ADR_GPIO_TYPE3 0x66U /* agpio [0:7] */
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/**
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* @brief Reg addr: GPIO PULL_UP_PULL_DOWN (R/W)
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*/
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#define MFXSTM32L152_REG_ADR_GPIO_PUPD1 0x68U /* gpio [0:7] */
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#define MFXSTM32L152_REG_ADR_GPIO_PUPD2 0x69U /* gpio [8:15] */
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#define MFXSTM32L152_REG_ADR_GPIO_PUPD3 0x6AU /* agpio [0:7] */
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/**
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* @brief Reg addr: GPIO SET (W): When GPIO is in output mode, write (1) puts
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the corresponding GPO in High level.
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*/
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#define MFXSTM32L152_REG_ADR_GPO_SET1 0x6CU /* gpio [0:7] */
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#define MFXSTM32L152_REG_ADR_GPO_SET2 0x6DU /* gpio [8:15] */
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#define MFXSTM32L152_REG_ADR_GPO_SET3 0x6EU /* agpio [0:7] */
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/**
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* @brief Reg addr: GPIO CLEAR (W): When GPIO is in output mode, write (1) puts
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the corresponding GPO in Low level.
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*/
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#define MFXSTM32L152_REG_ADR_GPO_CLR1 0x70U /* gpio [0:7] */
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#define MFXSTM32L152_REG_ADR_GPO_CLR2 0x71U /* gpio [8:15] */
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#define MFXSTM32L152_REG_ADR_GPO_CLR3 0x72U /* agpio [0:7] */
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/**
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* @brief Reg addr: GPIO STATE (R): Give state of the GPIO pin.
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*/
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#define MFXSTM32L152_REG_ADR_GPIO_STATE1 0x10U /* gpio [0:7] */
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#define MFXSTM32L152_REG_ADR_GPIO_STATE2 0x11U /* gpio [8:15] */
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#define MFXSTM32L152_REG_ADR_GPIO_STATE3 0x12U /* agpio [0:7] */
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/* GPIOs can INDIVIDUALLY generate interruption to the Main MCU thanks to the MFXSTM32L152_IRQ_OUT signal */
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/* the general MFXSTM32L152_IRQ_GPIO_SRC_EN shall be enabled too */
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/* GPIO IRQ_GPI_SRC1/2/3 (R/W): registers enable or not the feature to generate irq */
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#define MFXSTM32L152_REG_ADR_IRQ_GPI_SRC1 0x48U /* gpio [0:7] */
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#define MFXSTM32L152_REG_ADR_IRQ_GPI_SRC2 0x49U /* gpio [8:15] */
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#define MFXSTM32L152_REG_ADR_IRQ_GPI_SRC3 0x4AU /* agpio [0:7] */
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/**
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* @brief GPIO IRQ_GPI_EVT1/2/3 (R/W): Irq generated on level (0) or edge (1).
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*/
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#define MFXSTM32L152_REG_ADR_IRQ_GPI_EVT1 0x4CU /* gpio [0:7] */
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#define MFXSTM32L152_REG_ADR_IRQ_GPI_EVT2 0x4DU /* gpio [8:15] */
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#define MFXSTM32L152_REG_ADR_IRQ_GPI_EVT3 0x4EU /* agpio [0:7] */
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/**
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* @brief GPIO IRQ_GPI_TYPE1/2/3 (R/W): Irq generated on (0) : Low level or Falling edge.
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(1) : High level or Rising edge.
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*/
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#define MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE1 0x50U /* gpio [0:7] */
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#define MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE2 0x51U /* gpio [8:15] */
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#define MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE3 0x52U /* agpio [0:7] */
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/**
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* @brief GPIO IRQ_GPI_PENDING1/2/3 (R): irq occurs
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*/
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#define MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING1 0x0CU /* gpio [0:7] */
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#define MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING2 0x0DU /* gpio [8:15] */
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#define MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING3 0x0EU /* agpio [0:7] */
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/**
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* @brief GPIO IRQ_GPI_ACK1/2/3 (W): Write (1) to acknowledge IRQ event
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*/
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#define MFXSTM32L152_REG_ADR_IRQ_GPI_ACK1 0x54U /* gpio [0:7] */
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#define MFXSTM32L152_REG_ADR_IRQ_GPI_ACK2 0x55U /* gpio [8:15] */
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#define MFXSTM32L152_REG_ADR_IRQ_GPI_ACK3 0x56U /* agpio [0:7] */
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/**
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* @brief Touch Screen Registers
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*/
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#define MFXSTM32L152_TS_SETTLING 0xA0U
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#define MFXSTM32L152_TS_TOUCH_DET_DELAY 0xA1U
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#define MFXSTM32L152_TS_AVE 0xA2U
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#define MFXSTM32L152_TS_TRACK 0xA3U
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#define MFXSTM32L152_TS_FIFO_TH 0xA4U
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#define MFXSTM32L152_TS_FIFO_STA 0x20U
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#define MFXSTM32L152_TS_FIFO_LEVEL 0x21U
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#define MFXSTM32L152_TS_XY_DATA 0x24U
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/**
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* @brief Register address: Idd control register (R/W)
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*/
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#define MFXSTM32L152_REG_ADR_IDD_CTRL 0x80U
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/**
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* @brief Register address: Idd pre delay register (R/W)
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*/
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#define MFXSTM32L152_REG_ADR_IDD_PRE_DELAY 0x81U
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/**
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* @brief Register address: Idd Shunt registers (R/W)
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*/
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#define MFXSTM32L152_REG_ADR_IDD_SHUNT0_MSB 0x82U
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#define MFXSTM32L152_REG_ADR_IDD_SHUNT0_LSB 0x83U
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#define MFXSTM32L152_REG_ADR_IDD_SHUNT1_MSB 0x84U
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#define MFXSTM32L152_REG_ADR_IDD_SHUNT1_LSB 0x85U
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#define MFXSTM32L152_REG_ADR_IDD_SHUNT2_MSB 0x86U
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#define MFXSTM32L152_REG_ADR_IDD_SHUNT2_LSB 0x87U
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#define MFXSTM32L152_REG_ADR_IDD_SHUNT3_MSB 0x88U
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#define MFXSTM32L152_REG_ADR_IDD_SHUNT3_LSB 0x89U
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#define MFXSTM32L152_REG_ADR_IDD_SHUNT4_MSB 0x8AU
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#define MFXSTM32L152_REG_ADR_IDD_SHUNT4_LSB 0x8BU
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/**
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* @brief Register address: Idd ampli gain register (R/W)
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*/
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#define MFXSTM32L152_REG_ADR_IDD_GAIN_MSB 0x8CU
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#define MFXSTM32L152_REG_ADR_IDD_GAIN_LSB 0x8DU
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/**
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* @brief Register address: Idd VDD min register (R/W)
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*/
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#define MFXSTM32L152_REG_ADR_IDD_VDD_MIN_MSB 0x8EU
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#define MFXSTM32L152_REG_ADR_IDD_VDD_MIN_LSB 0x8FU
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/**
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* @brief Register address: Idd value register (R)
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*/
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#define MFXSTM32L152_REG_ADR_IDD_VALUE_MSB 0x14U
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#define MFXSTM32L152_REG_ADR_IDD_VALUE_MID 0x15U
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#define MFXSTM32L152_REG_ADR_IDD_VALUE_LSB 0x16U
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/**
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* @brief Register address: Idd calibration offset register (R)
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*/
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#define MFXSTM32L152_REG_ADR_IDD_CAL_OFFSET_MSB 0x18U
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#define MFXSTM32L152_REG_ADR_IDD_CAL_OFFSET_LSB 0x19U
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/**
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* @brief Register address: Idd shunt used offset register (R)
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*/
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#define MFXSTM32L152_REG_ADR_IDD_SHUNT_USED 0x1AU
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/**
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* @brief Register address: shunt stabilisation delay registers (R/W)
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*/
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#define MFXSTM32L152_REG_ADR_IDD_SH0_STABILIZATION 0x90U
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#define MFXSTM32L152_REG_ADR_IDD_SH1_STABILIZATION 0x91U
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#define MFXSTM32L152_REG_ADR_IDD_SH2_STABILIZATION 0x92U
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#define MFXSTM32L152_REG_ADR_IDD_SH3_STABILIZATION 0x93U
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#define MFXSTM32L152_REG_ADR_IDD_SH4_STABILIZATION 0x94U
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/**
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* @brief Register address: Idd number of measurements register (R/W)
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*/
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#define MFXSTM32L152_REG_ADR_IDD_NBR_OF_MEAS 0x96U
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/**
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* @brief Register address: Idd delta delay between 2 measurements register (R/W)
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*/
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#define MFXSTM32L152_REG_ADR_IDD_MEAS_DELTA_DELAY 0x97U
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/**
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* @brief Register address: Idd number of shunt on board register (R/W)
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*/
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#define MFXSTM32L152_REG_ADR_IDD_SHUNTS_ON_BOARD 0x98U
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/**
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* @}
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*/
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/** @addtogroup MFXSTM32L152_Exported_Types
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* @{
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*/
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typedef int32_t (*MFXSTM32L152_Write_Func)(void *, uint16_t, uint8_t*, uint16_t);
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typedef int32_t (*MFXSTM32L152_Read_Func) (void *, uint16_t, uint8_t*, uint16_t);
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typedef struct
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{
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MFXSTM32L152_Write_Func WriteReg;
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MFXSTM32L152_Read_Func ReadReg;
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void *handle;
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/* Internal resources */
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} mfxstm32l152_ctx_t;
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/**
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* @}
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*/
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/** @addtogroup MFXSTM32L152_Exported_Functions
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* @{
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*/
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int32_t mfxstm32l152_write_reg(mfxstm32l152_ctx_t *ctx, uint16_t reg, uint8_t *data, uint16_t length);
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int32_t mfxstm32l152_read_reg(mfxstm32l152_ctx_t *ctx, uint16_t reg, uint8_t *data, uint16_t length);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* MFXSTM32L152_REG_H */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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