`timescale 1ns / 1ps

module del_meas #(
	parameter WIDTH = 10
)(
	input wire clk,						// clock
	input wire rst,						// reset
	
	input wire ref,						// reference signal
	input wire sig,						// signal being measured
	
	input wire arm,						// arm the next measurement cycle
	output wire listening,				// indicated that measurement is armed
	output reg done,						// signals when measurement has concluded
	input wire ack,						// acknowledge latest measurement, turn off done
	
	output reg negative,					// indicates if delay is negative
	output reg [WIDTH-1:0] delay		// delay in ticks
);

// named states
localparam S_IDLE = 2'b0;
localparam S_LISTEN = 2'b1;

// inner state
reg [1:0] state;

// main state machine
always@(posedge clk)
begin
	if (rst)
	begin
		done <= 0;
		negative <= 0;
		delay <= 0;
		state <= S_IDLE;
	end
	else
	begin
		
	end
end

// output logic
assign listening = (state == S_LISTEN);

endmodule
