`timescale 1ns / 1ps
module jitmeas_top(
	input wire clk50M, // 50MHz clock input
	input wire rstbt,
	
	//output wire clk200M
	output wire [16:4] aio
);

wire rst = ~rstbt;

/* Main Clock Generation module */
wire main_pll_locked;
wire clk200M;

MainPLL main_pll (
	 // Clock in ports
    .In_50MHz(clk50M),      		// IN

    // Clock out ports
    .Out_200MHz(clk200M),     	// OUT
	 
    // Status and control signals
    .RESET(rst),						// IN
    .LOCKED(main_pll_locked)		// OUT
);      

localparam MAIN_CLK_FREQ = 200; // Main Clock Frequency in MHz

assign aio[16:5] = 0;

eth_mac eth_mac_inst (
    .clk(clk200M), 
    .rst(rst), 
	 
    .REF_CLK(REF_CLK), 
    
	 //.TXEN(TXEN), 
    //.TXD(TXD), 
    
	 .CRS_DV(0), 
    .RXD(0)
);

endmodule
