`timescale 1ns / 1ps

`include "src/eth/mac_memory_access_controller.v"
`include "src/rmii/rmii_transmit_controller.v"

module eth_mac #( 
	parameter MEM_DATA_WIDTH = 8,
	parameter MEM_ADDR_WIDTH = 12,
	
	// AUTOCALCULATED
	parameter MEM_ADDR_MSB = MEM_ADDR_WIDTH - 1,
	parameter LEN_WIDTH = 11,
	parameter LEN_MSB = LEN_WIDTH - 1,
	parameter CTRL_WORD_WIDTH = 32
)(
	input clk, rst, clear,

	input [MEM_DATA_WIDTH-1:0] mem_data,
	output [MEM_ADDR_WIDTH-1:0] mem_addr,
	
	input [CTRL_WORD_WIDTH-1:0] ctrl_word,

	output TXEN,
	output [1:0] TXD	

	//input CRS_DV,
	//input [1:0] RXD
);

wire tx_wrt;
wire tx_not_full;
wire transmitter_busy;
wire [MEM_DATA_WIDTH-1:0] tx_data_in;

rmii_transmit_controller #(
	.STORAGE_WIDTH(MEM_DATA_WIDTH)
) tx_ctrl (
	.clk(clk),
	.rst(rst),
	.clear(clear),
	
	.data_in(tx_data_in),
	.wrt(tx_wrt),
	.not_full(tx_not_full),
	.busy(transmitter_busy),
	
	.TXEN(TXEN),
	.TXD(TXD)
);

wire [MEM_ADDR_MSB:0] frame_addr = ctrl_word[MEM_ADDR_WIDTH-1:0];
wire [LEN_MSB:0] frame_len = ctrl_word[MEM_ADDR_WIDTH + LEN_WIDTH - 1:MEM_ADDR_WIDTH];
wire start = ctrl_word[CTRL_WORD_WIDTH - 1];

//wire mem_acc_busy;

mac_memory_access_controller #(
	.DATA_WIDTH(MEM_DATA_WIDTH),
	.ADDR_WIDTH(MEM_ADDR_WIDTH)
) mem_acc_ctrl (
	.clk(clk),
	.rst(rst),
	.clear(clear),
	
	.mem_data(mem_data),
	.mem_addr(mem_addr),
	
	.transmitter_busy(transmitter_busy),
	.start(start),
	.frame_addr(frame_addr),
	.frame_len(frame_len),
	
	.busy(/*mem_acc_busy*/),
	.tx_data_in(tx_data_in),
	.tx_not_full(tx_not_full),
	.tx_wrt(tx_wrt)
);




endmodule
