`timescale 1ns / 1ps

`include "src/del_meas/del_meas.v"

module del_meas_test;

	// Inputs
	reg clk;
	reg rst;
	reg clear;
	reg ref;
	reg sig;
	reg arm;
	reg ack;

	// Outputs
	wire listening;
	wire done;
	wire negative;
	wire [9:0] delay;

	// Instantiate the Unit Under Test (UUT)
	del_meas uut (
		.clk(clk), 
		.rst(rst), 
		.clear(clear), 
		.ref(ref), 
		.sig(sig), 
		.arm(arm), 
		.listening(listening), 
		.done(done), 
		.ack(ack), 
		.negative(negative), 
		.delay(delay)
	);
	
	localparam CLK_PERIOD = 5;
	localparam CLK_HALFPERIOD = 5 / 2.0;
	always #(CLK_HALFPERIOD) clk <= ~clk;
	
	reg sclk;
	always #10 sclk <= ~sclk;

	reg start;

	integer signed_delay;
	
	always @(posedge sclk)
	begin
		if (done || start)
		begin
			if (done)
			begin
				signed_delay = delay;
				if (negative) signed_delay = -signed_delay;
				signed_delay = signed_delay * CLK_PERIOD;
				$display("%d", signed_delay);
				ack <= 1;
			end
			arm <= 1;
		end
		else
		begin
			ack <= 0;
			arm <= 0;
		end
	end

	initial begin
		// Initialize Inputs
		clk <= 0;
		rst <= 1;
		clear <= 0;
		ref <= 0;
		sig <= 0;
		arm <= 0;
		ack <= 0;
		
		sclk <= 0;
		signed_delay = 0;
		start <= 0;

		// Wait 20 ns for global reset to finish
		#20;
		rst <= 0;
		
		#20;
		start <= 1;
		
		@(posedge sclk);
		start <= 0;
		
		#20;
		ref <= 1;
		
		#50;
		sig <= 1;
		
		#30;
		ref <= 0;
		
		#40;
		sig <= 0;
		
		#50;
		sig <= 1;
		
		#25;
		ref <= 1;
		
		#50;
		sig <= 0;
		ref <= 0;
		
		#20;
		  
		// Add stimulus here
		$finish;
	end
      
endmodule

