`timescale 1ns / 1ps

module top_sim;

	// Inputs
	reg clk50M;
	reg rstbt;

	// Outputs
	wire [16:4] aio;

	// Instantiate the Unit Under Test (UUT)
	jitmeas_top uut (
		.clk50M(clk50M), 
		.rstbt(rstbt), 
		.aio(aio)
	);

	always #10 clk50M = ~clk50M;

	initial begin
		// Initialize Inputs
		clk50M = 0; 
		rstbt = 1;

		// Wait 100 ns for global reset to finish
		#20;
        
		// Add stimulus here 
		rstbt = 0;
	end
      
endmodule

