`timescale 1ns / 1ps

module rmii_clock_generator #(
	parameter MAIN_CLK_FREQ = 200, // frequency of the main clock
	
	// AUTOCALCULATED
	parameter DIV_RATIO = (MAIN_CLK_FREQ / 50),	// division ratio
	parameter CNTR_WIDTH = $clog2(DIV_RATIO), // width of the CNTR
	parameter CNTR_MSB = CNTR_WIDTH - 1			// index of the counter's MSB
)(
	input wire clk,				// main clock input
	input wire rst,				// synchronous reset
	
	output wire REF_CLK, 		// RMII REF_CLK output
	output wire rising			// the next clk cycle comes with a rising edge on the REF_CLK
//	output wire falling			// ... falling ...
);

reg [CNTR_MSB:0] ref_clk_cntr;
always @(posedge clk)
begin
	if (rst)
	begin
		ref_clk_cntr <= 0;
	end
	else
	begin
		if (ref_clk_cntr == (DIV_RATIO - 1'b1))
		begin
			ref_clk_cntr <= 0;
		end
		else
		begin
			ref_clk_cntr <= ref_clk_cntr + 1'b1;
		end
	end
end

assign REF_CLK = ref_clk_cntr;
assign rising = !ref_clk_cntr;

endmodule
