`timescale 1ns / 1ps

`include "src/clkdiv.v"

module clk_div_test;

	// Inputs
	reg clk;
	reg rst;
	reg clear;

	// Outputs
	wire pos;
	wire neg;
	wire sclk;

	// Instantiate the Unit Under Test (UUT)
	clkdiv #(
		.DIV(4)
	) uut (
		.clk(clk), 
		.rst(rst), 
		.clear(clear), 
		.pos(pos), 
		.neg(neg),
		.sclk(sclk)
	);

	always #10 clk <= ~clk;

	initial begin
		// Initialize Inputs
		clk <= 0;
		rst <= 1;
		clear <= 0;

		// Wait 100 ns for global reset to finish
		#20;
      rst <= 0;
		 
		// Add stimulus here
		#1000;
		
		$finish;
	end
      
endmodule

