`timescale 1ns / 1ps

module logsys_xc6_top(
	input clk50M, // 50MHz clock input
	input rstbt,
	
	inout [16:4] aio,
	input [2:0] bt,
	
	output cpld_mosi,
	input cpld_miso,
	output cpld_load,
	output cpld_clk,
	output cpld_rstn,
	output cpld_jtagen
);


assign cpld_jtagen = 1'b0;

wire rst = ~rstbt;

/* Main Clock Generation module */
wire clk50M90;
wire clk50M0;
wire clk200M;

MainPLL main_pll (
	 // Clock in ports
    .In_50MHz(clk50M),      		// IN

    // Clock out ports
	 .Out_50MHz_0(clk50M0),
    .Out_50MHz_90(clk50M90),     	// OUT
	 .Out_200MHz(clk200M),
	 
    // Status and control signals
    .RESET(rst)						// IN
//    .LOCKED(/*main_pll_locked*/)		// OUT
);

/* CPLD IO controller */
wire [7:0] sw;
wire [7:0] leds;

io_controller io_ctrl_inst (
	.clk(clk50M90),
	.rst(rst),
	.clear(1'b0),
	
	.leds(leds),
	.sw(sw),
	
	.mosi(cpld_mosi),
	.miso(cpld_miso),
	.load(cpld_load),
	.sclk(cpld_clk),
	.rstn(cpld_rstn)
);

ODDR2 ref_clk_oddr (
	.D0(1'b1),
	.D1(1'b0),
	.R(1'b0),
	.S(1'b0),
	.CE(1'b1),
	.C0(clk50M0),
	.C1(~clk50M0),
	.Q(aio[12])
);

/* signals */
wire [1:0] TXD;
wire TXEN;
//wire [1:0] RXD;
//wire CRS_DV;

/* pins */

// Unused pins
assign aio[14] = 1'b0;
//assign aio[10] = 1'b0;
//assign aio[8] = 1'b0;
assign aio[6] = 1'b0;
assign aio[5] = 1'b0;
assign aio[4] = 1'b0;

// Inputs
//assign RXD[0] = aio[11];
//assign RXD[1] = aio[9];
//assign CRS_DV = aio[7];
assign aio[11] = 1'b0;
assign aio[9] = 1'b0;
assign aio[7] = 1'b0;

// Outputs
assign aio[16] = TXD[0];
assign aio[15] = TXD[1];
assign aio[13] = TXEN;
//assign aio[12] = REF_CLK;
//assign aio[12] = clk50M0;


/* input synchronization */
wire sig;
wire ref;
wire [2:0] bt_synced;

isync ref_isync (
	.clk(clk200M),
	.rst(rst),
	
	.in(aio[8]),
	.out(ref)
);

isync sig_isync (
	.clk(clk200M),
	.rst(rst),
	
	.in(aio[10]),
	.out(sig)
);

isync #(
	.WIDTH(3)
) btn_isync (
	.clk(clk50M90),
	.rst(rst),
	
	.in(bt),
	.out(bt_synced)
);

/* JitMeas module */
jitmeas_top jitmeas_inst (
	.clk50(clk50M90),
	.clk200(clk200M),
	.rst(rst),
	.clear(1'b0),
	
	.btn(bt_synced),
	.leds(leds),
	.sw(sw),
	
	.sig(sig),
	.ref(ref),
	
	//.RXD(RXD),
	//.CRS_DV(CRS_DV),
	
	.TXD(TXD),
	.TXEN(TXEN)
);

endmodule
