`timescale 1ns / 1ps
module rmii_controller #(
	parameter MAIN_CLK_FREQ = 200
)(
	input wire clk,
	input wire rst,
	
	/* RMII signals */
	
	// reference clock
	output wire REF_CLK,
	
	// transmit signals
	output wire [1:0] TXD,
	output wire TXEN,
	
	// receive signals
	input wire [1:0] RXD,
	input wire CRS_DV
);


/* RMII Reference Clock Generation state machine */
wire ref_clk_rising;
wire ref_clk_falling;
rmii_clock_generator #(
	.MAIN_CLK_FREQ(MAIN_CLK_FREQ)
) clk_gen (
	.clk(clk),
	.rst(rst),
	
	.REF_CLK(REF_CLK),
	.rising(ref_clk_rising),
	.falling(ref_clk_falling)
);

/*  */
assign TXD = 0;
assign TXEN = 0;



endmodule
