`timescale 1ns / 1ps

`include "src/eth/crc32.v"

module crc32_test;

	// Inputs
	reg clk;
	reg rst;
	reg clear;
	reg [7:0] data_in;
	reg crc_en;

	// Outputs
	wire [31:0] crc_out;

	// Instantiate the Unit Under Test (UUT)
	crc32 uut (
		.clk(clk), 
		.rst(rst), 
		.clear(clear), 
		.data_in(data_in), 
		.crc_en(crc_en), 
		.crc_out(crc_out)
	);
	
	always #10 clk = ~clk;

	integer ifile;
	integer c;

	initial begin
		// Initialize Inputs
		clk = 0;
		rst = 1;
		clear = 0;
		data_in = 0;
		crc_en = 0;

		// Wait 100 ns for global reset to finish
		#100;
		rst = 0;
        
		// Add stimulus here
		
		// open file holding the test input
		ifile = $fopen("src/sim/lorem_ipsum.txt", "r");
		if (ifile == 0)
		begin
			$display("Error on opening test input!\n");
			$finish;
		end
		
		while (!$feof(ifile))
		begin
			@(posedge clk);
			c = $fgetc(ifile);
			if (c != -1)
			begin
				data_in = c[7:0];
				crc_en = 1;
				$display("%c", data_in);
			end
			else
			begin
				crc_en = 0;
			end
		end
		
		$fclose(ifile);
		
		#100;
		
		$finish;
	end
      
endmodule

