`timescale 1ns / 1ps

module isync #(
	parameter STAGES = 3,
	parameter WIDTH = 1,
	
	// AUTOCALCULATED
	parameter GEN_STAGES = STAGES - 1,
	parameter GEN_STAGES_MSB = STAGES - 2
)(
	input clk, rst,
	input [WIDTH-1:0] in,
	output [WIDTH-1:0] out
);

(* iob="force" *)
reg [WIDTH-1:0] first;

reg [WIDTH-1:0] stages[GEN_STAGES_MSB:0];

integer i;
always @(posedge clk)
begin
	if (rst)
	begin
		first <= 0;
		for (i = 0; i < GEN_STAGES; i = i + 1)
		begin
			stages[i] <= 0;
		end
	end
	else
	begin
		first <= in;
		stages[0] <= first;
		
		for (i = 1; i < GEN_STAGES; i = i + 1)
		begin
			stages[i] <= stages[i - 1];
		end		
	end
end

assign out = stages[GEN_STAGES_MSB];

endmodule
