`timescale 1ns / 1ps

module io_controller_test;
	
	reg [7:0] SW;
	reg [7:0] LEDS;
	reg [3:0] IDX;

	// Inputs
	reg clk;
	reg rst;
	reg clear;
	reg [7:0] leds;

	// Outputs
	wire [7:0] sw;
	wire mosi;
	wire miso;
	wire load;
	wire sclk;
	wire rstn;

	// Instantiate the Unit Under Test (UUT)
	io_controller #(
		.CLK_DIV(4)
	) uut (
		.clk(clk), 
		.rst(rst), 
		.clear(clear), 
		.leds(leds), 
		.sw(sw), 
		.mosi(mosi), 
		.miso(miso), 
		.load(load), 
		.sclk(sclk), 
		.rstn(rstn)
	);

	always #1 clk <= ~clk;

	always @(posedge load)
	begin
		SW <= $random;
		leds <= $random;
	end
	
	assign miso = work[0];
	
	reg [15:0] work;
	always @(posedge sclk)
	begin
		if (rst)
		begin
			work <= 16'h0000;
			IDX <= 0;
		end
		else
		begin
			work <= {mosi, work[15:1]};
			IDX <= IDX + 1;
			if (load)
			begin
				LEDS <= work[8:1];
				work <= {8'b0, SW};
				IDX <= 0;
			end
		end
	end

	initial begin
		// Initialize Inputs
		clk <= 0;
		rst <= 1;
		clear <= 0;
		leds <= $random | 1;
		
		LEDS <= 0;
		SW <= $random | 1;
		IDX <= 0;
		work <= 0;

		// Wait 100 ns for global reset to finish
		#2;
		rst <= 0;
        
		// Add stimulus here		
		#1000;
		
		$finish;
	end
      
endmodule

