`timescale 1ns / 1ps

module clkdiv #(
	parameter DIV = 2,
	
	// AUTOCALCULATED
	parameter HALFDIV = DIV / 2,
	parameter CNTR_MSB = $clog2(DIV) - 1
)(
	input clk, rst, clear, // general signals
	output pos, neg, // output strobes corresponding to rising and falling edges
	output sclk // output clock
);

wire rstclr = rst || clear;
reg [CNTR_MSB:0] cntr;

always @(posedge clk)
begin
	if (rstclr)
	begin
		cntr <= 0;
	end
	else
	begin
		if (cntr == (DIV - 1'b1))
		begin
			cntr <= 0;
		end
		else
		begin
			cntr <= cntr + 1'b1;
		end
	end
end

assign sclk = cntr < HALFDIV;
assign pos = cntr == 0;
assign neg = cntr == HALFDIV;


endmodule
