`timescale 1ns / 1ps

module logsys_xc6_top(
	input wire clk50M, // 50MHz clock input
	input wire rstbt,
	
	inout wire [16:4] aio,
	input wire [0:0] bt
);

wire rst = ~rstbt;

/* Main Clock Generation module */
wire clk50M90;
wire clk50M0;

MainPLL main_pll (
	 // Clock in ports
    .In_50MHz(clk50M),      		// IN

    // Clock out ports
	 .Out_50MHz_0(clk50M0),
    .Out_50MHz_90(clk50M90),     	// OUT
	 
    // Status and control signals
    .RESET(rst)						// IN
//    .LOCKED(/*main_pll_locked*/)		// OUT
);

/* signals */
wire [1:0] TXD;
wire TXEN, REF_CLK;
//wire [1:0] RXD;
//wire CRS_DV;

/* pins */

// Unused pins
assign aio[14] = 1'b0;
assign aio[12] = 1'b0;
assign aio[10] = 1'b0;
assign aio[8] = 1'b0;
assign aio[6] = 1'b0;
assign aio[4] = 1'b0;

// Inputs
//assign RXD[0] = aio[11];
//assign RXD[1] = aio[9];
//assign CRS_DV = aio[7];
//
//assign aio[11] = 1'bZ;
//assign aio[9] = 1'bZ;
//assign aio[7] = 1'bZ;

assign aio[11] = 1'b0;
assign aio[9] = 1'b0;
assign aio[7] = 1'b0;

// Outputs
assign aio[16] = TXD[0];
assign aio[15] = TXD[1];
assign aio[13] = TXEN;
//assign aio[5] = REF_CLK;
assign aio[5] = clk50M0;

/* JitMeas module */
jitmeas_top jitmeas_inst (
	.clk50(clk50M90),
	.rst(rst),
	.clear(1'b0),
	
	.btn(bt[0]),
	
	.REF_CLK(REF_CLK),
	//.RXD(RXD),
	//.CRS_DV(CRS_DV),
	
	.TXD(TXD),
	.TXEN(TXEN)
);

endmodule
