`timescale 1ns / 1ps

`include "src/eth/eth_mac.v"

module jitmeas_top(
	input clk50, rst, clear,
	
	input btn,
	
	output REF_CLK,
	//input [1:0] RXD,
	//input CRS_DV,
	output [1:0] TXD,
	output TXEN
);

localparam MAIN_CLK_FREQ = 150; 	// Main Clock Frequency in MHz
localparam MEM_DATA_WIDTH = 8;	// Memory word size
localparam MEM_ADDR_WIDTH = 12;	// Memory address size

wire [MEM_DATA_WIDTH-1:0] stream_mem_data;
wire [MEM_ADDR_WIDTH-1:0] stream_mem_addr;

wire [31:0] ctrl_word;

eth_mac #(
	.MEM_DATA_WIDTH(MEM_DATA_WIDTH),
	.MEM_ADDR_WIDTH(MEM_ADDR_WIDTH)
) eth_mac_inst (
    .clk(clk50), 
    .rst(rst),
	 .clear(1'b0),
	 
	 .mem_data(stream_mem_data),
	 .mem_addr(stream_mem_addr),
	 
	 .ctrl_word(ctrl_word),
	 
	 .TXEN(TXEN),
	 .TXD(TXD)
);

StreamMemory stream_mem (
	/* PORT A */
  .clka(clk50), // input clka
  
  .ena(1'b0), 			// input ena
  .wea(1'b0), 			// input [0 : 0] wea
  .addra(12'b0), 	// input [10 : 0] addra
  .dina(8'b0), 	// input [7 : 0] dina

	/* PORT B */
  .clkb(clk50), 		// input clkb
  .rstb(rst), 		// input rstb
  .addrb(stream_mem_addr), 		// input [10 : 0] addrb
  .doutb(stream_mem_data) 			// output [7 : 0] doutb
);

/* button handling */
reg btn_prev;
always @(posedge clk50)
begin
	if (rst | clear)
	begin
		btn_prev <= 0;
	end
	else
	begin
		btn_prev <= btn;
	end
end

localparam FRAME_LENGTH = 100;

assign ctrl_word[30:0] = 31'b0 | (FRAME_LENGTH << MEM_ADDR_WIDTH) | (0);
assign ctrl_word[31] = ~btn_prev && btn;

assign REF_CLK = clk50;

endmodule
