From 895d5fc0de76435ab8a5e0d5911bcb1a0e63a78d Mon Sep 17 00:00:00 2001 From: Epagris Date: Thu, 5 Dec 2024 09:57:10 +0100 Subject: [PATCH] operational --- .gitignore | 3 + src/cdc.v | 27 ++ src/clkdiv.v | 42 ++ src/del_meas/del_meas.v | 117 ++++- src/del_meas/del_meas_cdc.v | 65 +++ src/eth/eth_mac.v | 1 - src/eth/mac_memory_access_controller.v | 43 +- src/io_controller.v | 93 ++++ src/isync.v | 46 ++ src/jitmeas_top.v | 209 +++++++- src/packetizer.v | 109 +++++ src/port/logsys_xc6_top.v | 108 ++++- src/rmii/rmii_transmit_controller.v | 2 +- src/sim/clk_div_test.v | 48 ++ src/sim/del_meas_test.v | 122 +++++ src/sim/eth_mac_test.v | 2 +- src/sim/frame_recv.txt | 1 + src/sim/io_controller_test.v | 93 ++++ src/sim/rmii_transmit_controller_test.v | 1 - src/stream_mem_init.cgf | 448 +++++++++++++++++- ... => stream_mem_init_lorem_ipsum_frame.coe} | 0 wcfg/crc32.wcfg | 46 ++ wcfg/del_meas.wcfg | 144 ++++++ wcfg/eth_mac.wcfg | 158 ++++++ wcfg/fifo.wcfg | 160 +++++++ wcfg/io_controller.wcfg | 126 +++++ wcfg/rmii_ctrl.wcfg | 79 +++ wcfg/rmii_tx_ctrl.wcfg | 245 ++++++++++ 28 files changed, 2465 insertions(+), 73 deletions(-) create mode 100644 .gitignore create mode 100644 src/cdc.v create mode 100644 src/clkdiv.v create mode 100644 src/del_meas/del_meas_cdc.v create mode 100644 src/io_controller.v create mode 100644 src/isync.v create mode 100644 src/packetizer.v create mode 100644 src/sim/clk_div_test.v create mode 100644 src/sim/del_meas_test.v create mode 100644 src/sim/frame_recv.txt create mode 100644 src/sim/io_controller_test.v rename src/{lorem_ipsum_frame.coe => stream_mem_init_lorem_ipsum_frame.coe} (100%) create mode 100644 wcfg/crc32.wcfg create mode 100644 wcfg/del_meas.wcfg create mode 100644 wcfg/eth_mac.wcfg create mode 100644 wcfg/fifo.wcfg create mode 100644 wcfg/io_controller.wcfg create mode 100644 wcfg/rmii_ctrl.wcfg create mode 100644 wcfg/rmii_tx_ctrl.wcfg diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..8e5b280 --- /dev/null +++ b/.gitignore @@ -0,0 +1,3 @@ +*.out +*.vcd +*.sav diff --git a/src/cdc.v b/src/cdc.v new file mode 100644 index 0000000..158912c --- /dev/null +++ b/src/cdc.v @@ -0,0 +1,27 @@ +`timescale 1ns / 1ps + +module cdc ( + input tclk, // target domain's clock + input rst, + + input sin, // input data from the source domain + output tout // output data to the target domain +); + +reg [1:0] pipe; +always @(posedge tclk) +begin + if (rst) + begin + pipe <= 0; + end + else + begin + pipe[0] <= sin; + pipe[1] <= pipe[0]; + end +end + +assign tout = pipe[1]; + +endmodule diff --git a/src/clkdiv.v b/src/clkdiv.v new file mode 100644 index 0000000..9b616c1 --- /dev/null +++ b/src/clkdiv.v @@ -0,0 +1,42 @@ +`timescale 1ns / 1ps + +module clkdiv #( + parameter DIV = 2, + + // AUTOCALCULATED + parameter HALFDIV = DIV / 2, + parameter CNTR_MSB = $clog2(DIV) - 1 +)( + input clk, rst, clear, // general signals + output pos, neg, // output strobes corresponding to rising and falling edges + output sclk // output clock +); + +wire rstclr = rst || clear; +reg [CNTR_MSB:0] cntr; + +always @(posedge clk) +begin + if (rstclr) + begin + cntr <= 0; + end + else + begin + if (cntr == (DIV - 1'b1)) + begin + cntr <= 0; + end + else + begin + cntr <= cntr + 1'b1; + end + end +end + +assign sclk = cntr < HALFDIV; +assign pos = cntr == 0; +assign neg = cntr == HALFDIV; + + +endmodule diff --git a/src/del_meas/del_meas.v b/src/del_meas/del_meas.v index cffcad5..7d6b208 100644 --- a/src/del_meas/del_meas.v +++ b/src/del_meas/del_meas.v @@ -1,47 +1,130 @@ `timescale 1ns / 1ps module del_meas #( - parameter WIDTH = 10 + parameter WIDTH = 10, + + // AUTOCALCULATED + parameter DEL_MAX_TICK = (1 << WIDTH) - 1 // maximum delay that can be handled )( - input wire clk, // clock - input wire rst, // reset + input clk, // clock + input rst, // reset + input clear, // clear - input wire ref, // reference signal - input wire sig, // signal being measured + input ref, // reference signal + input sig, // signal being measured - input wire arm, // arm the next measurement cycle - output wire listening, // indicated that measurement is armed - output reg done, // signals when measurement has concluded - input wire ack, // acknowledge latest measurement, turn off done + input arm, // arm the next measurement cycle + output listening, // indicates that measurement is armed + output done, // signals when measurement has concluded + input ack, // acknowledge latest measurement, turn off done output reg negative, // indicates if delay is negative - output reg [WIDTH-1:0] delay // delay in ticks + output reg [WIDTH-1:0] delay, // delay in ticks + + output [2:0] state_dbg ); -// named states -localparam S_IDLE = 2'b0; -localparam S_LISTEN = 2'b1; +wire rstclr = rst || clear; -// inner state -reg [1:0] state; +// named states +localparam S_IDLE = 3'b001; +localparam S_LISTEN = 3'b010; +localparam S_MEASURE = 3'b100; + +// first edge associations +localparam FE_REF = 1'b0; +localparam FE_SIG = 1'b1; + +reg [2:0] state; // FSM state + +reg arm_prev, ref_prev, sig_prev, ack_prev; // various input values in the previous cycle +wire arm_edge = arm && !arm_prev; // there was a transition on the arm input +wire ref_edge = !ref && ref_prev; // there was a transition in the reference +wire sig_edge = !sig && sig_prev; // there was a transition in the signal + +reg first_edge; // stores the signal transitioned first +wire end_meas = (first_edge == FE_REF) ? sig_edge : ref_edge; // end meas pulse +wire ack_pulse = ack && !ack_prev; // ack line has been pulsed + +reg acked; // acknowledge in the previous cycle, used for done masking // main state machine always@(posedge clk) begin - if (rst) + if (rstclr) begin - done <= 0; negative <= 0; delay <= 0; + + arm_prev <= 0; + ref_prev <= 0; + sig_prev <= 0; + state <= S_IDLE; + first_edge <= FE_REF; + acked <= 1; + ack_prev <= 0; end else begin + // retain specific inputs + arm_prev <= arm; + ref_prev <= ref; + sig_prev <= sig; + ack_prev <= ack; + // save acknowledgement + if (ack_pulse) + begin + acked <= 1; + end + + // delay counter with saturation + if ((state == S_MEASURE) && (delay < DEL_MAX_TICK)) + begin + delay <= delay + 1'b1; + end + + // state machine + case (state) + S_IDLE: if (arm_edge) state <= S_LISTEN; + S_LISTEN: + if (sig_edge || ref_edge) + begin + delay <= 0; // reset the delay + + if (sig_edge && ref_edge) // both signals transitioned in the same time slot + begin + negative <= 0; + state <= S_IDLE; + acked <= 0; + end + else // only a single transision was detected + begin + state <= S_MEASURE; + first_edge <= sig_edge ? FE_SIG : FE_REF; // store which signal produced the first edge + negative <= sig_edge; // delay is negative, if signal edge comes first + end + end + S_MEASURE: + if (end_meas) + begin + state <= S_IDLE; + acked <= 0; + end + default: + begin + state <= S_IDLE; + acked <= 0; + end + endcase end end // output logic assign listening = (state == S_LISTEN); +assign done = (state == S_IDLE) && (!acked); + +assign state_dbg = state; endmodule diff --git a/src/del_meas/del_meas_cdc.v b/src/del_meas/del_meas_cdc.v new file mode 100644 index 0000000..2ddea58 --- /dev/null +++ b/src/del_meas/del_meas_cdc.v @@ -0,0 +1,65 @@ +`timescale 1ns / 1ps + +`include "src/del_meas/del_meas.v" + +module del_meas_cdc #( + parameter WIDTH = 10 +)( + input clkMeas, clkIntf, rst, clear, + input ref, sig, arm, ack, + output listening, done, negative, [WIDTH-1:0] delay, [2:0]state_dbg +); + +wire arm_M, ack_M, listening_M, done_M; + +cdc arm_cdc ( + .tclk(clkMeas), + .rst(rst), + .sin(arm), + .tout(arm_M) +); + +cdc ack_cdc ( + .tclk(clkMeas), + .rst(rst), + .sin(ack), + .tout(ack_M) +); + +cdc listening_cdc ( + .tclk(clkIntf), + .rst(rst), + .sin(listening_M), + .tout(listening) +); + +cdc done_cdc ( + .tclk(clkIntf), + .rst(rst), + .sin(done_M), + .tout(done) +); + +del_meas #( + .WIDTH(WIDTH) +) del_meas_nocdc ( + .clk(clkMeas), + .rst(rst), + .clear(clear), + + .ref(ref), + .sig(sig), + + .arm(arm_M), + .listening(listening_M), + .done(done_M), + .ack(ack_M), + + .negative(negative), + .delay(delay), + + .state_dbg(state_dbg) +); + + +endmodule diff --git a/src/eth/eth_mac.v b/src/eth/eth_mac.v index 33d788e..a592832 100644 --- a/src/eth/eth_mac.v +++ b/src/eth/eth_mac.v @@ -1,7 +1,6 @@ `timescale 1ns / 1ps `include "src/eth/mac_memory_access_controller.v" -`include "src/rmii/rmii_clock_generator.v" `include "src/rmii/rmii_transmit_controller.v" module eth_mac #( diff --git a/src/eth/mac_memory_access_controller.v b/src/eth/mac_memory_access_controller.v index 7f1dcc8..3e73012 100644 --- a/src/eth/mac_memory_access_controller.v +++ b/src/eth/mac_memory_access_controller.v @@ -9,7 +9,8 @@ module mac_memory_access_controller #( // AUTOCALCULATED parameter DATA_MSB = DATA_WIDTH - 1, parameter ADDR_MSB = ADDR_WIDTH - 1, - parameter LEN_MSB = 10 + parameter LEN_MSB = 10, + parameter MIN_FRAME_SIZE = 6'd60 )( input clk, rst, clear, // general signals @@ -31,15 +32,25 @@ module mac_memory_access_controller #( // -------------- wire clear_crc = (state == IDLE); -wire crc_en = (state == FETCH_FRAME) && tx_not_full; +wire crc_en = ((state == FETCH_FRAME) || (state == INSERT_PADDING)) && tx_not_full; wire [31:0] crc_out; +// override CRC input when zero padding is applied +reg [DATA_WIDTH-1:0] crc_in; +always @(*) +begin + case (state) + INSERT_PADDING: crc_in <= 8'h00; + default: crc_in <= mem_data; + endcase +end + crc32 crc32_engine ( .clk(clk), .rst(rst), .clear(clear_crc | clear), - .data_in(mem_data), + .data_in(crc_in), .crc_en(crc_en), .crc_out(crc_out) ); @@ -52,8 +63,9 @@ wire rstclr = rst | clear; localparam IDLE = 0; localparam INSERT_PREAMBLE = 1; localparam FETCH_FRAME = 2; -localparam APPEND_CRC = 3; -localparam WAIT_TX_COMPL = 4; +localparam INSERT_PADDING = 3; +localparam APPEND_CRC = 4; +localparam WAIT_TX_COMPL = 5; // main state machine reg [2:0] state; @@ -67,6 +79,7 @@ reg [2:0] preamble_idx; // index of the preamble byte being sent reg [1:0] crc_idx; // index of the CRC bytes reg [LEN_MSB:0] len_left; // remaining bytes to be transmitted +reg [5:0] pad_left; // padding left always @(posedge clk) begin @@ -78,6 +91,7 @@ begin len_left <= 0; preamble_idx <= 0; crc_idx <= 0; + pad_left <= 0; end else begin @@ -88,6 +102,7 @@ begin len_left <= frame_len - 1'b1; preamble_idx <= 0; crc_idx <= 0; + pad_left <= (frame_len < MIN_FRAME_SIZE) ? (MIN_FRAME_SIZE - frame_len - 1'b1) : 0; end INSERT_PREAMBLE: @@ -109,6 +124,14 @@ begin end end end + + INSERT_PADDING: + begin + if (tx_not_full) + begin + pad_left <= pad_left - 1'b1; + end + end APPEND_CRC: begin @@ -125,8 +148,9 @@ begin // next state logic case (state) IDLE: if (start && frame_params_valid) state <= INSERT_PREAMBLE; - INSERT_PREAMBLE: if (preamble_idx == (PREAMBLE_LEN - 1)) state <= FETCH_FRAME; - FETCH_FRAME: if ((len_left == 0) && tx_not_full) state <= APPEND_CRC; + INSERT_PREAMBLE: if ((preamble_idx == (PREAMBLE_LEN - 1)) && tx_not_full) state <= FETCH_FRAME; + FETCH_FRAME: if ((len_left == 0) && tx_not_full) begin if (pad_left != 0) state <= INSERT_PADDING; else state <= APPEND_CRC; end + INSERT_PADDING: if ((pad_left == 0) && tx_not_full) state <= APPEND_CRC; APPEND_CRC: if ((crc_idx == (3)) && tx_not_full) state <= WAIT_TX_COMPL; WAIT_TX_COMPL: if (!transmitter_busy) state <= IDLE; default: state <= IDLE; @@ -137,13 +161,14 @@ end // combinatorial outputs assign busy = (state != IDLE); //assign tx_data_in = mem_data; -assign tx_wrt = (state == FETCH_FRAME) || (state == INSERT_PREAMBLE) || (state == APPEND_CRC); +assign tx_wrt = (state == INSERT_PREAMBLE) || (state == FETCH_FRAME) || (state == INSERT_PADDING) || (state == APPEND_CRC); // assign data output always @(*) begin case (state) - INSERT_PREAMBLE: tx_data_in <= (preamble_idx == (PREAMBLE_LEN - 1)) ? SOF_PATTERN : PREAMBLE_PATTERN; + INSERT_PREAMBLE: tx_data_in <= (preamble_idx == (PREAMBLE_LEN - 1'b1)) ? SOF_PATTERN : PREAMBLE_PATTERN; + INSERT_PADDING: tx_data_in <= 8'h00; APPEND_CRC: case (crc_idx) 2'd3: tx_data_in <= crc_out[31:24]; diff --git a/src/io_controller.v b/src/io_controller.v new file mode 100644 index 0000000..b45a37c --- /dev/null +++ b/src/io_controller.v @@ -0,0 +1,93 @@ +`timescale 1ns / 1ps + +`include "src/clkdiv.v" + +module io_controller #( + parameter CLK_DIV = 100, + parameter FRAME_SIZE = 16, + + // AUTOCALCULATED + parameter FRAME_IDX_MSB = $clog2(FRAME_SIZE - 1) - 1 +)( + input clk, rst, clear, + input [7:0] leds, + output reg [7:0] sw, + + output mosi, + input miso, + output load, + output sclk, + output rstn +); + +wire rstclr = rst || clear; + +wire strobe; + +clkdiv #( + .DIV(CLK_DIV) +) sclk_div ( + .clk(clk), + .rst(rst), + .clear(clear), + + .sclk(sclk), + .pos(), + .neg(strobe) +); + +reg [FRAME_SIZE-1:0] data; +reg [FRAME_IDX_MSB:0] idx; + +always @(posedge clk) +begin + if (rstclr) + begin + data <= 0; + sw <= 0; + end + else + begin + if (strobe) + begin + if (idx == (FRAME_SIZE - 1'b1)) + begin + sw <= data[7:0]; + data <= {miso, 7'b0, leds}; + end + else + begin + data <= {miso, data[15:1]}; + end + end + end +end + +always @(posedge clk) +begin + if (rstclr) + begin + idx <= (FRAME_SIZE - 1'b1); + end + else + begin + if (strobe) + begin + if (idx == (FRAME_SIZE - 1'b1)) + begin + idx <= 0; + end + else + begin + idx <= idx + 1'b1; + end + end + end +end + +assign rstn = !rstclr; +assign load = idx == (FRAME_SIZE - 1'b1); +assign mosi = data[0]; + + +endmodule diff --git a/src/isync.v b/src/isync.v new file mode 100644 index 0000000..5fdb2c3 --- /dev/null +++ b/src/isync.v @@ -0,0 +1,46 @@ +`timescale 1ns / 1ps + +module isync #( + parameter STAGES = 3, + parameter WIDTH = 1, + + // AUTOCALCULATED + parameter GEN_STAGES = STAGES - 1, + parameter GEN_STAGES_MSB = STAGES - 2 +)( + input clk, rst, + input [WIDTH-1:0] in, + output [WIDTH-1:0] out +); + +(* iob="force" *) +reg [WIDTH-1:0] first; + +reg [WIDTH-1:0] stages[GEN_STAGES_MSB:0]; + +integer i; +always @(posedge clk) +begin + if (rst) + begin + first <= 0; + for (i = 0; i < GEN_STAGES; i = i + 1) + begin + stages[i] <= 0; + end + end + else + begin + first <= in; + stages[0] <= first; + + for (i = 1; i < GEN_STAGES; i = i + 1) + begin + stages[i] <= stages[i - 1]; + end + end +end + +assign out = stages[GEN_STAGES_MSB]; + +endmodule diff --git a/src/jitmeas_top.v b/src/jitmeas_top.v index a0f42c9..b46d84d 100644 --- a/src/jitmeas_top.v +++ b/src/jitmeas_top.v @@ -1,27 +1,73 @@ `timescale 1ns / 1ps `include "src/eth/eth_mac.v" +`include "src/del_meas/del_meas_cdc.v" module jitmeas_top( - input clk50, rst, clear, + input clk50, clk200, rst, clear, - input btn, + input [2:0] btn, + output [7:0] leds, + input [7:0] sw, - output REF_CLK, //input [1:0] RXD, //input CRS_DV, output [1:0] TXD, - output TXEN + output TXEN, + + input sig, ref ); -localparam MAIN_CLK_FREQ = 150; // Main Clock Frequency in MHz +/* configuration */ localparam MEM_DATA_WIDTH = 8; // Memory word size localparam MEM_ADDR_WIDTH = 12; // Memory address size +localparam DM_WIDTH = 7; // Width of the delay measurement counter +localparam FRAME_LENGTH = 2; // Frame payload size +/* LEDs and switches */ +assign leds = {sig_synced, ref_synced, pckt_full, pckt_empty, dm_state, dm_enable}; + +/* SIG and REF signals synchronized to the default domain */ +wire sig_synced, ref_synced; + +cdc sig_jm_cdc ( + .tclk(clk50), + .rst(rst), + .sin(sig), + .tout(sig_synced) +); + +cdc ref_jm_cdc ( + .tclk(clk50), + .rst(rst), + .sin(ref), + .tout(ref_synced) +); + +/* Data stream memory */ wire [MEM_DATA_WIDTH-1:0] stream_mem_data; wire [MEM_ADDR_WIDTH-1:0] stream_mem_addr; +wire stream_mem_wea; +wire [MEM_ADDR_WIDTH-1:0] stream_mem_addra; +wire [MEM_DATA_WIDTH-1:0] stream_mem_dina; -wire [31:0] ctrl_word; +StreamMemory stream_mem ( + /* PORT A */ + .clka(clk50), // input clka + + .wea(stream_mem_wea), // input [0 : 0] wea + .addra(stream_mem_addra), // input [10 : 0] addra + .dina(stream_mem_dina), // input [15 : 0] dina + + /* PORT B */ + .clkb(clk50), // input clkb + .rstb(rst), // input rstb + .addrb(stream_mem_addr), // input [11 : 0] addrb + .doutb(stream_mem_data) // output [7 : 0] doutb +); + +/* Ethernet MAC */ +wire [31:0] mac_ctrl_word; eth_mac #( .MEM_DATA_WIDTH(MEM_DATA_WIDTH), @@ -34,30 +80,55 @@ eth_mac #( .mem_data(stream_mem_data), .mem_addr(stream_mem_addr), - .ctrl_word(ctrl_word), + .ctrl_word(mac_ctrl_word), .TXEN(TXEN), .TXD(TXD) ); -StreamMemory stream_mem ( - /* PORT A */ - .clka(clk50), // input clka - - .ena(1'b0), // input ena - .wea(1'b0), // input [0 : 0] wea - .addra(12'b0), // input [10 : 0] addra - .dina(8'b0), // input [7 : 0] dina +/* transmission scheduler and packetizer */ +reg [MEM_DATA_WIDTH-1:0] pckt_data_in; +wire pckt_wrt; +wire pckt_immtx; +wire pckt_empty; +wire pckt_full; - /* PORT B */ - .clkb(clk50), // input clkb - .rstb(rst), // input rstb - .addrb(stream_mem_addr), // input [10 : 0] addrb - .doutb(stream_mem_data) // output [7 : 0] doutb +packetizer #( + .MEM_WRITE_WIDTH(MEM_DATA_WIDTH), + .MEM_DEPTH_BYTE(2**MEM_ADDR_WIDTH) +) tx_packetizer ( + .clk(clk50), + .rst(rst), + .clear(clear), + + .mac_ctrl_word(mac_ctrl_word), + + .data_in(pckt_data_in), + .wrt(pckt_wrt), + + .mem_wea(stream_mem_wea), + .mem_data(stream_mem_dina), + .mem_addr(stream_mem_addra), + + .immtx(pckt_immtx), + .empty(pckt_empty), + .full(pckt_full) +); + +clkdiv #( + .DIV(25000000) +) pckt_tx_sched ( + .clk(clk50), + .rst(rst), + .clear(clear), + + .sclk(), + .pos(pckt_immtx), + .neg() ); /* button handling */ -reg btn_prev; +reg [2:0] btn_prev; always @(posedge clk50) begin if (rst | clear) @@ -70,11 +141,99 @@ begin end end -localparam FRAME_LENGTH = 100; +//reg mac_transmit; +//assign mac_ctrl_word[30:0] = 31'b0 | (FRAME_LENGTH << MEM_ADDR_WIDTH) | (0); +//assign mac_ctrl_word[31] = (~btn_prev[0] && btn[0]) | mac_transmit; + +/* measurement handling */ +wire dm_start = ~btn_prev[1] && btn[1]; +wire dm_enable = sw[0]; + +reg dm_arm; +wire dm_done; +reg dm_ack; +wire [2:0] dm_state; +wire dm_negative; +wire [DM_WIDTH-1:0] dm_delay; + +del_meas_cdc #( + .WIDTH(DM_WIDTH) +) del_meas_inst ( + .clkMeas(clk200), + .clkIntf(clk50), + .rst(rst), + .clear(clear), + + .ref(ref), + .sig(sig), + + .arm(dm_arm), + .listening(), + .done(dm_done), + .ack(dm_ack), + + .negative(dm_negative), + .delay(dm_delay), + + .state_dbg(dm_state) +); + +/* measurement data handling */ + +// convert delay to a signed value +wire [DM_WIDTH:0] signed_delay = dm_negative ? (~({1'b0, dm_delay} + 1'b1)) : {1'b0, dm_delay}; + +reg dm_done_prev; +assign pckt_wrt = dm_done && !dm_done_prev; + +always @(posedge clk50) +begin + if (rst) + begin + pckt_data_in <= 0; + + dm_done_prev <= 0; + dm_ack <= 0; + dm_arm <= 0; + end + else + begin + // retain states + dm_done_prev <= dm_done; + + // measurement done + if (dm_done) + begin + pckt_data_in <= signed_delay; + + dm_ack <= 1; + end + else + begin + dm_ack <= 0; + dm_arm <= 0; + end + + // start button is pressed + if (dm_start) + begin + dm_arm <= 1; + end + + // ----------------- + + // data is written to the memory + if (pckt_wrt) + begin + if (dm_enable) + begin + dm_arm <= 1; + end + end + end +end + -assign ctrl_word[30:0] = 31'b0 | (FRAME_LENGTH << MEM_ADDR_WIDTH) | (0); -assign ctrl_word[31] = ~btn_prev && btn; -assign REF_CLK = clk50; endmodule diff --git a/src/packetizer.v b/src/packetizer.v new file mode 100644 index 0000000..2a09ef0 --- /dev/null +++ b/src/packetizer.v @@ -0,0 +1,109 @@ +`timescale 1ns / 1ps + +module packetizer #( + parameter MEM_WRITE_WIDTH = 16, // write size of the memory + //parameter MEM_READ_WIDTH = 8, + parameter MEM_DEPTH_BYTE = 1024, // depth of the memory in bytes + parameter MAX_PACKET_SIZE = 1500, + + // AUTOCALCULATED + parameter MEM_WRITE_MSB = MEM_WRITE_WIDTH - 1, + //parameter MEM_READ_MSB = MEM_READ_WIDTH - 1, + parameter MEM_DEPTH_MSB = $clog2(MEM_DEPTH_BYTE) - 1 +)( + input clk, rst, clear, // general signals + + output [31:0] mac_ctrl_word, // MAC control word + + input [MEM_WRITE_MSB:0] data_in, // data input + input wrt, // write signal + + output mem_wea, // memory write enable signal + output [MEM_WRITE_MSB:0] mem_data, // data going into the memory + output [MEM_DEPTH_MSB:0] mem_addr, // write address + + input immtx, // trigger an immediate transmission of memory contents + + output empty, // memory is empty + output full // memory is fully occupied +); + +wire rstclr = rst || clear; // combined reset and clear + +reg [MEM_DEPTH_MSB:0] wr_ptr; // write pointer +reg [MEM_DEPTH_MSB:0] rd_ptr; // read pointer + +reg [MEM_DEPTH_MSB+1:0] level; // fill level +always @(*) +begin + if (wr_ptr < rd_ptr) + level <= {1'b0, wr_ptr} + MEM_DEPTH_BYTE - {1'b0, rd_ptr}; // |===w-----r===| + else + level <= wr_ptr - rd_ptr; // |---r===w---| +end + +// write operations +always @(posedge clk) +begin + if (rstclr) + begin + wr_ptr <= 0; + end + else + begin + if (wrt && !full) // increase write pointer if possible + begin + wr_ptr <= wr_ptr + 1'b1; + end + end +end + +// read operations +wire level_triggers_transmit = (level > MAX_PACKET_SIZE - 1); +wire transmit = level_triggers_transmit || (immtx && !empty && !level_transmit); // level or demand-based transmission trigger + +always @(posedge clk) +begin + if (rstclr) + begin + rd_ptr <= 0; + end + else + begin + if (transmit) + begin + rd_ptr <= wr_ptr; + end + end +end + +reg level_transmit; + +always @(posedge clk) +begin + if (rstclr) + begin + level_transmit <= 0; + end + else + begin + if (level_triggers_transmit) + begin + level_transmit <= 1; + end + else if (immtx) + begin + level_transmit <= 0; + end + end +end + +// combinatorial outputs +assign empty = (rd_ptr == wr_ptr); +assign full = (wr_ptr == (rd_ptr - 1'b1)); +assign mem_wea = wrt && !full; +assign mem_data = data_in; +assign mem_addr = wr_ptr; +assign mac_ctrl_word = 0 | (transmit << 31) | (level << (MEM_DEPTH_MSB + 1)) | rd_ptr; + +endmodule diff --git a/src/port/logsys_xc6_top.v b/src/port/logsys_xc6_top.v index 24ec784..1dc35e9 100644 --- a/src/port/logsys_xc6_top.v +++ b/src/port/logsys_xc6_top.v @@ -1,18 +1,29 @@ `timescale 1ns / 1ps module logsys_xc6_top( - input wire clk50M, // 50MHz clock input - input wire rstbt, + input clk50M, // 50MHz clock input + input rstbt, - inout wire [16:4] aio, - input wire [0:0] bt + inout [16:4] aio, + input [2:0] bt, + + output cpld_mosi, + input cpld_miso, + output cpld_load, + output cpld_clk, + output cpld_rstn, + output cpld_jtagen ); + +assign cpld_jtagen = 1'b0; + wire rst = ~rstbt; /* Main Clock Generation module */ wire clk50M90; wire clk50M0; +wire clk200M; MainPLL main_pll ( // Clock in ports @@ -21,15 +32,46 @@ MainPLL main_pll ( // Clock out ports .Out_50MHz_0(clk50M0), .Out_50MHz_90(clk50M90), // OUT + .Out_200MHz(clk200M), // Status and control signals .RESET(rst) // IN // .LOCKED(/*main_pll_locked*/) // OUT ); +/* CPLD IO controller */ +wire [7:0] sw; +wire [7:0] leds; + +io_controller io_ctrl_inst ( + .clk(clk50M90), + .rst(rst), + .clear(1'b0), + + .leds(leds), + .sw(sw), + + .mosi(cpld_mosi), + .miso(cpld_miso), + .load(cpld_load), + .sclk(cpld_clk), + .rstn(cpld_rstn) +); + +ODDR2 ref_clk_oddr ( + .D0(1'b1), + .D1(1'b0), + .R(1'b0), + .S(1'b0), + .CE(1'b1), + .C0(clk50M0), + .C1(~clk50M0), + .Q(aio[12]) +); + /* signals */ wire [1:0] TXD; -wire TXEN, REF_CLK; +wire TXEN; //wire [1:0] RXD; //wire CRS_DV; @@ -37,21 +79,16 @@ wire TXEN, REF_CLK; // Unused pins assign aio[14] = 1'b0; -assign aio[12] = 1'b0; -assign aio[10] = 1'b0; -assign aio[8] = 1'b0; +//assign aio[10] = 1'b0; +//assign aio[8] = 1'b0; assign aio[6] = 1'b0; +assign aio[5] = 1'b0; assign aio[4] = 1'b0; // Inputs //assign RXD[0] = aio[11]; //assign RXD[1] = aio[9]; //assign CRS_DV = aio[7]; -// -//assign aio[11] = 1'bZ; -//assign aio[9] = 1'bZ; -//assign aio[7] = 1'bZ; - assign aio[11] = 1'b0; assign aio[9] = 1'b0; assign aio[7] = 1'b0; @@ -60,18 +97,55 @@ assign aio[7] = 1'b0; assign aio[16] = TXD[0]; assign aio[15] = TXD[1]; assign aio[13] = TXEN; -//assign aio[5] = REF_CLK; -assign aio[5] = clk50M0; +//assign aio[12] = REF_CLK; +//assign aio[12] = clk50M0; + + +/* input synchronization */ +wire sig; +wire ref; +wire [2:0] bt_synced; + +isync ref_isync ( + .clk(clk200M), + .rst(rst), + + .in(aio[8]), + .out(ref) +); + +isync sig_isync ( + .clk(clk200M), + .rst(rst), + + .in(aio[10]), + .out(sig) +); + +isync #( + .WIDTH(3) +) btn_isync ( + .clk(clk50M90), + .rst(rst), + + .in(bt), + .out(bt_synced) +); /* JitMeas module */ jitmeas_top jitmeas_inst ( .clk50(clk50M90), + .clk200(clk200M), .rst(rst), .clear(1'b0), - .btn(bt[0]), + .btn(bt_synced), + .leds(leds), + .sw(sw), + + .sig(sig), + .ref(ref), - .REF_CLK(REF_CLK), //.RXD(RXD), //.CRS_DV(CRS_DV), diff --git a/src/rmii/rmii_transmit_controller.v b/src/rmii/rmii_transmit_controller.v index 890ca27..403dd14 100644 --- a/src/rmii/rmii_transmit_controller.v +++ b/src/rmii/rmii_transmit_controller.v @@ -4,7 +4,7 @@ `include "src/rmii/rmii_serializer.v" module rmii_transmit_controller #( - parameter FIFO_DEPTH = 16, + parameter FIFO_DEPTH = 4, parameter STORAGE_WIDTH = 8, // AUTOCALCULATED diff --git a/src/sim/clk_div_test.v b/src/sim/clk_div_test.v new file mode 100644 index 0000000..351526d --- /dev/null +++ b/src/sim/clk_div_test.v @@ -0,0 +1,48 @@ +`timescale 1ns / 1ps + +`include "src/clkdiv.v" + +module clk_div_test; + + // Inputs + reg clk; + reg rst; + reg clear; + + // Outputs + wire pos; + wire neg; + wire sclk; + + // Instantiate the Unit Under Test (UUT) + clkdiv #( + .DIV(4) + ) uut ( + .clk(clk), + .rst(rst), + .clear(clear), + .pos(pos), + .neg(neg), + .sclk(sclk) + ); + + always #10 clk <= ~clk; + + initial begin + // Initialize Inputs + clk <= 0; + rst <= 1; + clear <= 0; + + // Wait 100 ns for global reset to finish + #20; + rst <= 0; + + // Add stimulus here + #1000; + + $finish; + end + +endmodule + diff --git a/src/sim/del_meas_test.v b/src/sim/del_meas_test.v new file mode 100644 index 0000000..0b0238c --- /dev/null +++ b/src/sim/del_meas_test.v @@ -0,0 +1,122 @@ +`timescale 1ns / 1ps + +`include "src/del_meas/del_meas.v" + +module del_meas_test; + + // Inputs + reg clk; + reg rst; + reg clear; + reg ref; + reg sig; + reg arm; + reg ack; + + // Outputs + wire listening; + wire done; + wire negative; + wire [9:0] delay; + + // Instantiate the Unit Under Test (UUT) + del_meas uut ( + .clk(clk), + .rst(rst), + .clear(clear), + .ref(ref), + .sig(sig), + .arm(arm), + .listening(listening), + .done(done), + .ack(ack), + .negative(negative), + .delay(delay) + ); + + localparam CLK_PERIOD = 5; + localparam CLK_HALFPERIOD = 5 / 2.0; + always #(CLK_HALFPERIOD) clk <= ~clk; + + reg sclk; + always #10 sclk <= ~sclk; + + reg start; + + integer signed_delay; + + always @(posedge sclk) + begin + if (done || start) + begin + if (done) + begin + signed_delay = delay; + if (negative) signed_delay = -signed_delay; + signed_delay = signed_delay * CLK_PERIOD; + $display("%d", signed_delay); + ack <= 1; + end + arm <= 1; + end + else + begin + ack <= 0; + arm <= 0; + end + end + + initial begin + // Initialize Inputs + clk <= 0; + rst <= 1; + clear <= 0; + ref <= 0; + sig <= 0; + arm <= 0; + ack <= 0; + + sclk <= 0; + signed_delay = 0; + start <= 0; + + // Wait 20 ns for global reset to finish + #20; + rst <= 0; + + #20; + start <= 1; + + @(posedge sclk); + start <= 0; + + #20; + ref <= 1; + + #50; + sig <= 1; + + #30; + ref <= 0; + + #40; + sig <= 0; + + #50; + sig <= 1; + + #25; + ref <= 1; + + #50; + sig <= 0; + ref <= 0; + + #20; + + // Add stimulus here + $finish; + end + +endmodule + diff --git a/src/sim/eth_mac_test.v b/src/sim/eth_mac_test.v index c2c5393..8317c1d 100644 --- a/src/sim/eth_mac_test.v +++ b/src/sim/eth_mac_test.v @@ -38,7 +38,7 @@ module eth_mac_test; // frame data localparam FRAME_ADDR = 0; - localparam FRAME_LENGTH = 100; + localparam FRAME_LENGTH = 10; localparam START = (1 << 31); // RMII deserializer diff --git a/src/sim/frame_recv.txt b/src/sim/frame_recv.txt new file mode 100644 index 0000000..c60e1a2 --- /dev/null +++ b/src/sim/frame_recv.txt @@ -0,0 +1 @@ +LLorem ipsum olor sit amet, consectetur adipiscing elit, sed do eiusmod tempor incididunt ut labore et dolore magna aliqua. Ut enim ad minim veniam, quis nostrud exercitation ullamco laboris nisi ut aliquip ex ea commodo consequat. Duis aute irure dolor in reprehenderit in voluptate velit esse cillum dolore eu fugiat nulla pariatur. Excepteur sint occaecat cupidatat non proident, sunt in culpa qui officia deserunt mollit anim id est laborum. diff --git a/src/sim/io_controller_test.v b/src/sim/io_controller_test.v new file mode 100644 index 0000000..6657983 --- /dev/null +++ b/src/sim/io_controller_test.v @@ -0,0 +1,93 @@ +`timescale 1ns / 1ps + +module io_controller_test; + + reg [7:0] SW; + reg [7:0] LEDS; + reg [3:0] IDX; + + // Inputs + reg clk; + reg rst; + reg clear; + reg [7:0] leds; + + // Outputs + wire [7:0] sw; + wire mosi; + wire miso; + wire load; + wire sclk; + wire rstn; + + // Instantiate the Unit Under Test (UUT) + io_controller #( + .CLK_DIV(4) + ) uut ( + .clk(clk), + .rst(rst), + .clear(clear), + .leds(leds), + .sw(sw), + .mosi(mosi), + .miso(miso), + .load(load), + .sclk(sclk), + .rstn(rstn) + ); + + always #1 clk <= ~clk; + + always @(posedge load) + begin + SW <= $random; + leds <= $random; + end + + assign miso = work[0]; + + reg [15:0] work; + always @(posedge sclk) + begin + if (rst) + begin + work <= 16'h0000; + IDX <= 0; + end + else + begin + work <= {mosi, work[15:1]}; + IDX <= IDX + 1; + if (load) + begin + LEDS <= work[8:1]; + work <= {8'b0, SW}; + IDX <= 0; + end + end + end + + initial begin + // Initialize Inputs + clk <= 0; + rst <= 1; + clear <= 0; + leds <= $random | 1; + + LEDS <= 0; + SW <= $random | 1; + IDX <= 0; + work <= 0; + + // Wait 100 ns for global reset to finish + #2; + rst <= 0; + + // Add stimulus here + #1000; + + $finish; + end + +endmodule + diff --git a/src/sim/rmii_transmit_controller_test.v b/src/sim/rmii_transmit_controller_test.v index 6abc5df..deace0d 100644 --- a/src/sim/rmii_transmit_controller_test.v +++ b/src/sim/rmii_transmit_controller_test.v @@ -1,7 +1,6 @@ `timescale 1ns / 500ps `include "src/rmii/rmii_transmit_controller.v" -`include "src/rmii/rmii_clock_generator.v" module rmii_transmit_controller_test; diff --git a/src/stream_mem_init.cgf b/src/stream_mem_init.cgf index 3be6cc4..f0e1fa4 100644 --- a/src/stream_mem_init.cgf +++ b/src/stream_mem_init.cgf @@ -1,5 +1,5 @@ #version3.0 -#memory_block_name=stream_init +#memory_block_name=lorem_ipsum_frame #block_depth=4096 #data_width=8 #default_word=0 @@ -10,4 +10,450 @@ #coe_radix=MEMORY_INITIALIZATION_RADIX #coe_data=MEMORY_INITIALIZATION_VECTOR #data= +@0 +4C +6F +72 +65 +6D +20 +69 +70 +73 +75 +6D +20 +64 +6F +6C +6F +72 +20 +73 +69 +74 +20 +61 +6D +65 +74 +2C +20 +63 +6F +6E +73 +65 +63 +74 +65 +74 +75 +72 +20 +61 +64 +69 +70 +69 +73 +63 +69 +6E +67 +20 +65 +6C +69 +74 +2C +20 +73 +65 +64 +20 +64 +6F +20 +65 +69 +75 +73 +6D +6F +64 +20 +74 +65 +6D +70 +6F +72 +20 +69 +6E +63 +69 +64 +69 +64 +75 +6E +74 +20 +75 +74 +20 +6C +61 +62 +6F +72 +65 +20 +65 +74 +20 +64 +6F +6C +6F +72 +65 +20 +6D +61 +67 +6E +61 +20 +61 +6C +69 +71 +75 +61 +2E +20 +55 +74 +20 +65 +6E +69 +6D +20 +61 +64 +20 +6D +69 +6E +69 +6D +20 +76 +65 +6E +69 +61 +6D +2C +20 +71 +75 +69 +73 +20 +6E +6F +73 +74 +72 +75 +64 +20 +65 +78 +65 +72 +63 +69 +74 +61 +74 +69 +6F +6E +20 +75 +6C +6C +61 +6D +63 +6F +20 +6C +61 +62 +6F +72 +69 +73 +20 +6E +69 +73 +69 +20 +75 +74 +20 +61 +6C +69 +71 +75 +69 +70 +20 +65 +78 +20 +65 +61 +20 +63 +6F +6D +6D +6F +64 +6F +20 +63 +6F +6E +73 +65 +71 +75 +61 +74 +2E +20 +44 +75 +69 +73 +20 +61 +75 +74 +65 +20 +69 +72 +75 +72 +65 +20 +64 +6F +6C +6F +72 +20 +69 +6E +20 +72 +65 +70 +72 +65 +68 +65 +6E +64 +65 +72 +69 +74 +20 +69 +6E +20 +76 +6F +6C +75 +70 +74 +61 +74 +65 +20 +76 +65 +6C +69 +74 +20 +65 +73 +73 +65 +20 +63 +69 +6C +6C +75 +6D +20 +64 +6F +6C +6F +72 +65 +20 +65 +75 +20 +66 +75 +67 +69 +61 +74 +20 +6E +75 +6C +6C +61 +20 +70 +61 +72 +69 +61 +74 +75 +72 +2E +20 +45 +78 +63 +65 +70 +74 +65 +75 +72 +20 +73 +69 +6E +74 +20 +6F +63 +63 +61 +65 +63 +61 +74 +20 +63 +75 +70 +69 +64 +61 +74 +61 +74 +20 +6E +6F +6E +20 +70 +72 +6F +69 +64 +65 +6E +74 +2C +20 +73 +75 +6E +74 +20 +69 +6E +20 +63 +75 +6C +70 +61 +20 +71 +75 +69 +20 +6F +66 +66 +69 +63 +69 +61 +20 +64 +65 +73 +65 +72 +75 +6E +74 +20 +6D +6F +6C +6C +69 +74 +20 +61 +6E +69 +6D +20 +69 +64 +20 +65 +73 +74 +20 +6C +61 +62 +6F +72 +75 +6D +2E #end diff --git a/src/lorem_ipsum_frame.coe b/src/stream_mem_init_lorem_ipsum_frame.coe similarity index 100% rename from src/lorem_ipsum_frame.coe rename to src/stream_mem_init_lorem_ipsum_frame.coe diff --git a/wcfg/crc32.wcfg b/wcfg/crc32.wcfg new file mode 100644 index 0000000..b086d0b --- /dev/null +++ b/wcfg/crc32.wcfg @@ -0,0 +1,46 @@ + + + + + + + + + + + + + + + crc_out[31:0] + crc_out[31:0] + HEXRADIX + false + + + clk + clk + + + rst + rst + + + clear + clear + + + data_in[7:0] + data_in[7:0] + ASCIIRADIX + + + crc_en + crc_en + + + ifile[31:0] + ifile[31:0] + HEXRADIX + + diff --git a/wcfg/del_meas.wcfg b/wcfg/del_meas.wcfg new file mode 100644 index 0000000..98f5a43 --- /dev/null +++ b/wcfg/del_meas.wcfg @@ -0,0 +1,144 @@ + + + + + + + + + + + + + + + listening + listening + + + done + done + + + negative + negative + + + delay[9:0] + delay[9:0] + + + clk + clk + + + rst + rst + + + clear + clear + + + ref + ref + + + sig + sig + + + arm + arm + + + ack + ack + + + sclk + sclk + + + start + start + + + signed_delay[31:0] + signed_delay[31:0] + SIGNEDDECRADIX + + + CLK_PERIOD[31:0] + CLK_PERIOD[31:0] + UNSIGNEDDECRADIX + + + CLK_HALFPERIOD + CLK_HALFPERIOD + + + DELMEAS + label + 128 128 255 + 230 230 230 + + + ref + ref + true + #ffff00 + + + ref_edge + ref_edge + + + sig + sig + true + #ffff00 + + + sig_edge + sig_edge + + + arm + arm + + + arm_edge + arm_edge + + + ack + ack + + + ack_pulse + ack_pulse + + + negative + negative + + + delay[9:0] + delay[9:0] + UNSIGNEDDECRADIX + + + listening + listening + + + done + done + + + state[3:0] + state[3:0] + UNSIGNEDDECRADIX + + diff --git a/wcfg/eth_mac.wcfg b/wcfg/eth_mac.wcfg new file mode 100644 index 0000000..8e32441 --- /dev/null +++ b/wcfg/eth_mac.wcfg @@ -0,0 +1,158 @@ + + + + + + + + + + + + + + + mem_data[7:0] + mem_data[7:0] + + + mem_data[7:0] + mem_data[7:0] + ASCIIRADIX + + + mem_addr[11:0] + mem_addr[11:0] + HEXRADIX + + + clk + clk + true + #ffff00 + + + rst + rst + + + TXEN + TXEN + + + TXD[1:0] + TXD[1:0] + + + deser[7:0] + deser[7:0] + HEXRADIX + + + deser[7:0] + deser[7:0] + ASCIIRADIX + + + ctrl_word[31:0] + ctrl_word[31:0] + + + label + mem[0:444,7:0] + mem[0:444,7:0] + mem[25:0,7:0] + ASCIIRADIX + + + MEM ACC CTRL + label + 128 128 255 + 230 230 230 + + + transmitter_busy + transmitter_busy + + + start + start + + + frame_addr[11:0] + frame_addr[11:0] + + + frame_len[10:0] + frame_len[10:0] + UNSIGNEDDECRADIX + + + busy + busy + + + tx_data_in[7:0] + tx_data_in[7:0] + ASCIIRADIX + + + tx_data_in[7:0] + tx_data_in[7:0] + HEXRADIX + + + tx_not_full + tx_not_full + + + tx_wrt + tx_wrt + + + state[2:0] + state[2:0] + UNSIGNEDDECRADIX + + + len_left[10:0] + len_left[10:0] + UNSIGNEDDECRADIX + + + crc_out[31:0] + crc_out[31:0] + HEXRADIX + + + SERIALIZER + label + 128 128 255 + 230 230 230 + + + mem[3:0,7:0] + mem[3:0,7:0] + ASCIIRADIX + + [3,7:0] + mem[3,7:0] + HEXRADIX + + + [2,7:0] + mem[2,7:0] + HEXRADIX + + + [1,7:0] + mem[1,7:0] + HEXRADIX + + + [0,7:0] + mem[0,7:0] + HEXRADIX + + + diff --git a/wcfg/fifo.wcfg b/wcfg/fifo.wcfg new file mode 100644 index 0000000..80a2caa --- /dev/null +++ b/wcfg/fifo.wcfg @@ -0,0 +1,160 @@ + + + + + + + + + + + + + + + clk + clk + + + rst + rst + + + out[7:0] + out[7:0] + ASCIIRADIX + true + #ff00ff + + + empty + empty + + + out_valid + out_valid + + + full + full + true + #ff0000 + + + clear + clear + + + in[7:0] + in[7:0] + ASCIIRADIX + true + #ffa500 + + + push + push + true + #ffff00 + + + pop + pop + true + #ffff00 + + + ifile[31:0] + ifile[31:0] + HEXRADIX + + + c[31:0] + c[31:0] + HEXRADIX + + + FIFO + label + 128 128 255 + 230 230 230 + + + mem[7:0,7:0] + mem[7:0,7:0] + ASCIIRADIX + + [7,7:0] + mem[7,7:0] + ASCIIRADIX + + + [6,7:0] + mem[6,7:0] + ASCIIRADIX + + + [5,7:0] + mem[5,7:0] + ASCIIRADIX + + + [4,7:0] + mem[4,7:0] + ASCIIRADIX + + + [3,7:0] + mem[3,7:0] + ASCIIRADIX + + + [2,7:0] + mem[2,7:0] + ASCIIRADIX + + + [1,7:0] + mem[1,7:0] + ASCIIRADIX + + + [0,7:0] + mem[0,7:0] + ASCIIRADIX + + + + push_idx[2:0] + push_idx[2:0] + UNSIGNEDDECRADIX + + + pop_idx[2:0] + pop_idx[2:0] + UNSIGNEDDECRADIX + + + level[3:0] + level[3:0] + UNSIGNEDDECRADIX + true + #00ffff + + + out_valid + out_valid + + + will_pop + will_pop + true + #ffff00 + + + will_push + will_push + true + #ffff00 + + diff --git a/wcfg/io_controller.wcfg b/wcfg/io_controller.wcfg new file mode 100644 index 0000000..5d4fa55 --- /dev/null +++ b/wcfg/io_controller.wcfg @@ -0,0 +1,126 @@ + + + + + + + + + + + + + + + clk + clk + + + sclk + sclk + + + rst + rst + + + mosi + mosi + + + miso + miso + true + #ffa500 + + + load + load + + + SW[7:0] + SW[7:0] + HEXRADIX + true + #00ffff + + + SW[7:0] + SW[7:0] + BINARYRADIX + true + #00ffff + + + LEDS[7:0] + LEDS[7:0] + HEXRADIX + true + #ffff00 + + + LEDS[7:0] + LEDS[7:0] + BINARYRADIX + true + #ffff00 + + + IDX[3:0] + IDX[3:0] + UNSIGNEDDECRADIX + + + clear + clear + + + sw[7:0] + sw[7:0] + + + work[15:0] + work[15:0] + HEXRADIX + + + IO CONTROLLER + label + 128 128 255 + 230 230 230 + + + data[15:0] + data[15:0] + HEXRADIX + + + data[15:0] + data[15:0] + BINARYRADIX + + + sw[7:0] + sw[7:0] + HEXRADIX + + + leds[7:0] + leds[7:0] + HEXRADIX + true + #ffff00 + + + leds[7:0] + leds[7:0] + BINARYRADIX + true + #ffff00 + + + idx[3:0] + idx[3:0] + UNSIGNEDDECRADIX + + diff --git a/wcfg/rmii_ctrl.wcfg b/wcfg/rmii_ctrl.wcfg new file mode 100644 index 0000000..50e22af --- /dev/null +++ b/wcfg/rmii_ctrl.wcfg @@ -0,0 +1,79 @@ + + + + + + + + + + + + + + + clk + clk + + + rst + rst + + + REF_CLK + REF_CLK + + + TXD[1:0] + TXD[1:0] + + + TXEN + TXEN + + + RMII_CLOCK_GENERATOR + label + 128 128 255 + 230 230 230 + + + clk + clk + + + rst + rst + + + REF_CLK + REF_CLK + + + rising + rising + + + falling + falling + + + ref_clk_cntr[1:0] + ref_clk_cntr[1:0] + + + MAIN_CLK_FREQ[31:0] + MAIN_CLK_FREQ[31:0] + UNSIGNEDDECRADIX + + + CNTR_WIDTH[31:0] + CNTR_WIDTH[31:0] + UNSIGNEDDECRADIX + + + CNTR_MSB[31:0] + CNTR_MSB[31:0] + UNSIGNEDDECRADIX + + diff --git a/wcfg/rmii_tx_ctrl.wcfg b/wcfg/rmii_tx_ctrl.wcfg new file mode 100644 index 0000000..266ed2e --- /dev/null +++ b/wcfg/rmii_tx_ctrl.wcfg @@ -0,0 +1,245 @@ + + + + + + + + + + + + + + + clk + clk + + + rst + rst + + + clear + clear + + + not_full + not_full + + + busy + busy + + + TXEN + TXEN + true + #ffff00 + + + TXD[1:0] + TXD[1:0] + true + #ffff00 + + + data_in[7:0] + data_in[7:0] + ASCIIRADIX + + + wrt + wrt + + + run + run + + + start + start + + + c[31:0] + c[31:0] + ASCIIRADIX + + + wrt_cntr[31:0] + wrt_cntr[31:0] + UNSIGNEDDECRADIX + + + deser[7:0] + deser[7:0] + BINARYRADIX + + + deser[7:0] + deser[7:0] + ASCIIRADIX + + + SERIALIZER + label + 128 128 255 + 230 230 230 + + + par_in[7:0] + par_in[7:0] + ASCIIRADIX + + + load + load + + + shift + shift + + + empty + empty + + + exhausted + exhausted + + + single + single + + + shift_work[7:0] + shift_work[7:0] + + + shift_work[7:0] + shift_work[7:0] + ASCIIRADIX + + + shift_count[1:0] + shift_count[1:0] + UNSIGNEDDECRADIX + + + FIFO + label + 128 128 255 + 230 230 230 + + + in[7:0] + in[7:0] + ASCIIRADIX + + + push + push + + + pop + pop + + + empty + empty + + + full + full + + + level[4:0] + level[4:0] + UNSIGNEDDECRADIX + + + mem[15:0,7:0] + mem[15:0,7:0] + ASCIIRADIX + + [15,7:0] + mem[15,7:0] + ASCIIRADIX + + + [14,7:0] + mem[14,7:0] + ASCIIRADIX + + + [13,7:0] + mem[13,7:0] + ASCIIRADIX + + + [12,7:0] + mem[12,7:0] + ASCIIRADIX + + + [11,7:0] + mem[11,7:0] + ASCIIRADIX + + + [10,7:0] + mem[10,7:0] + ASCIIRADIX + + + [9,7:0] + mem[9,7:0] + ASCIIRADIX + + + [8,7:0] + mem[8,7:0] + ASCIIRADIX + + + [7,7:0] + mem[7,7:0] + ASCIIRADIX + + + [6,7:0] + mem[6,7:0] + ASCIIRADIX + + + [5,7:0] + mem[5,7:0] + ASCIIRADIX + + + [4,7:0] + mem[4,7:0] + ASCIIRADIX + + + [3,7:0] + mem[3,7:0] + ASCIIRADIX + + + [2,7:0] + mem[2,7:0] + ASCIIRADIX + + + [1,7:0] + mem[1,7:0] + ASCIIRADIX + + + [0,7:0] + mem[0,7:0] + ASCIIRADIX + + +