- minor modifications

This commit is contained in:
Wiesner András 2024-11-16 09:37:11 +01:00
parent dcf2c2b808
commit 48a7ae54a3
3 changed files with 26 additions and 26 deletions

View File

@ -42,10 +42,8 @@ set(FLATUSB_SRC
usb.c
usb_callback_event.h
usb_common_defs.h
usb_common.h
usb_common_types.h
usb_core_types.h
usb_device_types.h
usb_driver.c
usb_driver.h

View File

@ -19,6 +19,10 @@
#define USB_STM32F4
#endif
#define USB_LINESPEED_FULL_SPEED (0b11)
#define USB_LINESPEED_FULL_SPEED_ULPI (0b01)
#define USB_LINESPEED_HIGH_SPEED_ULPI (0b00)
#define USBD ((USB_OTG_DeviceTypeDef *) (((uint32_t)(USBG)) + ((uint32_t)(USB_OTG_DEVICE_BASE))))
#define USBINEP ((USB_OTG_INEndpointTypeDef *) (((uint32_t)(USBG)) + ((uint32_t)(USB_OTG_IN_ENDPOINT_BASE))))
#define USBOUTEP ((USB_OTG_OUTEndpointTypeDef *) (((uint32_t)(USBG)) + ((uint32_t)(USB_OTG_OUT_ENDPOINT_BASE))))

View File

@ -17,49 +17,43 @@ __weak void usbdrv_ulpi_init() {
// ------------------------
#if USB_INTERNAL && USB_UPLI
#error "Select just one from USB_INTERNAL and USB_ULPI"
#endif
// initialize USB peripheral
void usbdrv_periph_init() {
// enable USB clock
USB_CLOCK_ENABLE();
// HAL_Delay(1000);
//__HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE();
//__HAL_RCC_USB_OTG_FS_FORCE_RESET();
//__HAL_RCC_USB_OTG_FS_RELEASE_RESET();
#if defined(USB_STM32H7)
// select either the internal or the external ULPI transceiver
#if USB_INTERNAL
SET_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_PHYSEL); // select the internal FS PHY
#endif
WAIT_FOR_nBIT_DELAY(USBG->GRSTCTL, USB_OTG_GRSTCTL_AHBIDL, 1);
SET_BIT(USBG->GRSTCTL, USB_OTG_GRSTCTL_CSRST); // reset the USB core
HAL_Delay(1);
WAIT_FOR_BIT_DELAY(USBG->GRSTCTL, USB_OTG_GRSTCTL_CSRST, 1);
#else
#if defined(USB_HIGH_SPEED)
#if USB_ULPI
CLEAR_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_PHYSEL); // select the external HS PHY
CLEAR_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_TSDPS);
CLEAR_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_ULPIFSLS);
CLEAR_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_ULPIEVBUSD);
CLEAR_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_ULPIEVBUSI);
// SET_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_PHYSEL);
SET_BIT(USBG->GRSTCTL, USB_OTG_GRSTCTL_CSRST); // reset USB core
HAL_Delay(1);
WAIT_FOR_BIT(USBG->GRSTCTL, USB_OTG_GRSTCTL_CSRST);
usbdrv_ulpi_init(); // initialize PHY
#endif
WAIT_FOR_nBIT_DELAY(USBG->GRSTCTL, USB_OTG_GRSTCTL_AHBIDL, 1); // wait for AHB transactions to cease
SET_BIT(USBG->GRSTCTL, USB_OTG_GRSTCTL_CSRST); // reset the USB core
WAIT_FOR_BIT_DELAY(USBG->GRSTCTL, USB_OTG_GRSTCTL_CSRST, 1);
#if USB_ULPI
usbdrv_ulpi_init(); // initialize PHY
#endif
CLEAR_BIT(USBG->GCCFG, USB_OTG_GCCFG_PWRDWN); // power the internal transceiver peripheral
CLEAR_BIT(USBG->GAHBCFG, USB_OTG_GAHBCFG_GINT); // mask all interrupts for now
CLEAR_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_HNPCAP | USB_OTG_GUSBCFG_SRPCAP); // disable HNP and SRP
WRITE_FIELD(USBG->GUSBCFG, USB_OTG_GUSBCFG_TRDT, TRDT_VALUE); // set TRDT according to the RM
// WRITE_FIELD(USBG->GUSBCFG, USB_OTG_GUSBCFG_TOCAL, TOCAL_VALUE); // set TOCAL
WRITE_FIELD(USBG->GUSBCFG, USB_OTG_GUSBCFG_TOCAL, TOCAL_VALUE); // set TOCAL
CLEAR_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_FHMOD); // clear Host mode forcing
SET_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_FDMOD); // force Device mode
@ -69,14 +63,18 @@ void usbdrv_periph_init() {
// SET_BIT(USBD->DCTL, USB_OTG_DCTL_SDIS); // soft disconnect peripheral (should be upper, but since it's controlled by a Device register, cannot be set before switching to device mode)
#if defined(USB_STM32H7)
#if !USB_VBUSSENSE
CLEAR_BIT(USBG->GCCFG, USB_OTG_GCCFG_VBDEN); // turn off VBUSSENSE
#endif
SET_BIT(USBG->GOTGCTL, USB_OTG_GOTGCTL_BVALOEN | USB_OTG_GOTGCTL_BVALOVAL); // force B-session
#elif defined(USB_STM32F4)
#if !USB_VBUSSENSE
SET_BIT(USBG->GCCFG, USB_OTG_GCCFG_NOVBUSSENS); // turn off VBUSSENSE
#endif
CLEAR_BIT(USBG->GCCFG, USB_OTG_GCCFG_VBUSBSEN | USB_OTG_GCCFG_VBUSASEN);
#endif
// HAL_Delay(50); // it takes time to forcing Device mode takes effect
HAL_Delay(25); // it takes time to forcing Device mode takes effect
#ifdef USB_HIGH_SPEED
// WRITE_FIELD(USBD->DCFG, USB_OTG_DCFG_DSPD, USB_LINESPEED_FULL_SPEED);