- minor modifications
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@ -42,10 +42,8 @@ set(FLATUSB_SRC
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usb.c
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usb_callback_event.h
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usb_common_defs.h
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usb_common.h
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usb_common_types.h
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usb_core_types.h
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usb_device_types.h
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usb_driver.c
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usb_driver.h
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@ -19,6 +19,10 @@
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#define USB_STM32F4
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#endif
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#define USB_LINESPEED_FULL_SPEED (0b11)
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#define USB_LINESPEED_FULL_SPEED_ULPI (0b01)
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#define USB_LINESPEED_HIGH_SPEED_ULPI (0b00)
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#define USBD ((USB_OTG_DeviceTypeDef *) (((uint32_t)(USBG)) + ((uint32_t)(USB_OTG_DEVICE_BASE))))
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#define USBINEP ((USB_OTG_INEndpointTypeDef *) (((uint32_t)(USBG)) + ((uint32_t)(USB_OTG_IN_ENDPOINT_BASE))))
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#define USBOUTEP ((USB_OTG_OUTEndpointTypeDef *) (((uint32_t)(USBG)) + ((uint32_t)(USB_OTG_OUT_ENDPOINT_BASE))))
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@ -17,49 +17,43 @@ __weak void usbdrv_ulpi_init() {
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// ------------------------
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#if USB_INTERNAL && USB_UPLI
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#error "Select just one from USB_INTERNAL and USB_ULPI"
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#endif
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// initialize USB peripheral
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void usbdrv_periph_init() {
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// enable USB clock
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USB_CLOCK_ENABLE();
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// HAL_Delay(1000);
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//__HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE();
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//__HAL_RCC_USB_OTG_FS_FORCE_RESET();
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//__HAL_RCC_USB_OTG_FS_RELEASE_RESET();
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#if defined(USB_STM32H7)
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// select either the internal or the external ULPI transceiver
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#if USB_INTERNAL
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SET_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_PHYSEL); // select the internal FS PHY
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#endif
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WAIT_FOR_nBIT_DELAY(USBG->GRSTCTL, USB_OTG_GRSTCTL_AHBIDL, 1);
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SET_BIT(USBG->GRSTCTL, USB_OTG_GRSTCTL_CSRST); // reset the USB core
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HAL_Delay(1);
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WAIT_FOR_BIT_DELAY(USBG->GRSTCTL, USB_OTG_GRSTCTL_CSRST, 1);
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#else
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#if defined(USB_HIGH_SPEED)
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#if USB_ULPI
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CLEAR_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_PHYSEL); // select the external HS PHY
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CLEAR_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_TSDPS);
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CLEAR_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_ULPIFSLS);
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CLEAR_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_ULPIEVBUSD);
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CLEAR_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_ULPIEVBUSI);
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// SET_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_PHYSEL);
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SET_BIT(USBG->GRSTCTL, USB_OTG_GRSTCTL_CSRST); // reset USB core
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HAL_Delay(1);
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WAIT_FOR_BIT(USBG->GRSTCTL, USB_OTG_GRSTCTL_CSRST);
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usbdrv_ulpi_init(); // initialize PHY
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#endif
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WAIT_FOR_nBIT_DELAY(USBG->GRSTCTL, USB_OTG_GRSTCTL_AHBIDL, 1); // wait for AHB transactions to cease
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SET_BIT(USBG->GRSTCTL, USB_OTG_GRSTCTL_CSRST); // reset the USB core
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WAIT_FOR_BIT_DELAY(USBG->GRSTCTL, USB_OTG_GRSTCTL_CSRST, 1);
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#if USB_ULPI
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usbdrv_ulpi_init(); // initialize PHY
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#endif
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CLEAR_BIT(USBG->GCCFG, USB_OTG_GCCFG_PWRDWN); // power the internal transceiver peripheral
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CLEAR_BIT(USBG->GAHBCFG, USB_OTG_GAHBCFG_GINT); // mask all interrupts for now
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CLEAR_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_HNPCAP | USB_OTG_GUSBCFG_SRPCAP); // disable HNP and SRP
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WRITE_FIELD(USBG->GUSBCFG, USB_OTG_GUSBCFG_TRDT, TRDT_VALUE); // set TRDT according to the RM
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// WRITE_FIELD(USBG->GUSBCFG, USB_OTG_GUSBCFG_TOCAL, TOCAL_VALUE); // set TOCAL
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WRITE_FIELD(USBG->GUSBCFG, USB_OTG_GUSBCFG_TOCAL, TOCAL_VALUE); // set TOCAL
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CLEAR_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_FHMOD); // clear Host mode forcing
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SET_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_FDMOD); // force Device mode
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@ -69,14 +63,18 @@ void usbdrv_periph_init() {
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// SET_BIT(USBD->DCTL, USB_OTG_DCTL_SDIS); // soft disconnect peripheral (should be upper, but since it's controlled by a Device register, cannot be set before switching to device mode)
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#if defined(USB_STM32H7)
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#if !USB_VBUSSENSE
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CLEAR_BIT(USBG->GCCFG, USB_OTG_GCCFG_VBDEN); // turn off VBUSSENSE
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#endif
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SET_BIT(USBG->GOTGCTL, USB_OTG_GOTGCTL_BVALOEN | USB_OTG_GOTGCTL_BVALOVAL); // force B-session
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#elif defined(USB_STM32F4)
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#if !USB_VBUSSENSE
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SET_BIT(USBG->GCCFG, USB_OTG_GCCFG_NOVBUSSENS); // turn off VBUSSENSE
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#endif
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CLEAR_BIT(USBG->GCCFG, USB_OTG_GCCFG_VBUSBSEN | USB_OTG_GCCFG_VBUSASEN);
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#endif
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// HAL_Delay(50); // it takes time to forcing Device mode takes effect
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HAL_Delay(25); // it takes time to forcing Device mode takes effect
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#ifdef USB_HIGH_SPEED
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// WRITE_FIELD(USBD->DCFG, USB_OTG_DCFG_DSPD, USB_LINESPEED_FULL_SPEED);
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