diff --git a/usb_common_defs.h b/usb_common_defs.h
index 8162e38..f5f6678 100644
--- a/usb_common_defs.h
+++ b/usb_common_defs.h
@@ -18,10 +18,10 @@
 
 #endif
 
-#define USBD ((USB_OTG_DeviceTypeDef *) ((uint32_t)(USBG) + (uint32_t)(USB_OTG_DEVICE_BASE)))
-#define USBINEP ((USB_OTG_INEndpointTypeDef *) ((uint32_t)(USBG) + (uint32_t)(USB_OTG_IN_ENDPOINT_BASE)))
-#define USBOUTEP ((USB_OTG_OUTEndpointTypeDef *) ((uint32_t)(USBG) + (uint32_t)(USB_OTG_OUT_ENDPOINT_BASE)))
-#define USBFIFO(ep) ((uint32_t *)((uint32_t)(USBG) + USB_OTG_FIFO_BASE + (USB_OTG_FIFO_SIZE) * (ep)))
-#define USBPCGCCTL ((uint32_t *)((uint32_t)(USBG) + USB_OTG_PCGCCTL_BASE))
+#define USBD ((USB_OTG_DeviceTypeDef *) (((uint32_t)(USBG)) + ((uint32_t)(USB_OTG_DEVICE_BASE))))
+#define USBINEP ((USB_OTG_INEndpointTypeDef *) (((uint32_t)(USBG)) + ((uint32_t)(USB_OTG_IN_ENDPOINT_BASE))))
+#define USBOUTEP ((USB_OTG_OUTEndpointTypeDef *) (((uint32_t)(USBG)) + ((uint32_t)(USB_OTG_OUT_ENDPOINT_BASE))))
+#define USBFIFO(ep) ((uint32_t *)(((uint32_t)(USBG)) + USB_OTG_FIFO_BASE + (USB_OTG_FIFO_SIZE) * (ep)))
+#define USBPCGCCTL ((uint32_t *)(((uint32_t)(USBG)) + USB_OTG_PCGCCTL_BASE))
 
 #endif /* CORE_USB_USB_COMMON_DEFS */
diff --git a/usb_driver.c b/usb_driver.c
index c8f75e7..9d1e962 100644
--- a/usb_driver.c
+++ b/usb_driver.c
@@ -45,14 +45,22 @@ static const char *FIFO_STATUS_STR[6] = {
 #if defined(USB_STM32H7)
 #define USB_GPIO_AF (GPIO_AF10_OTG2_FS)
 #elif defined(USB_STM32F4)
+#ifdef USB_HIGH_SPEED
+#define USB_GPIO_AF (GPIO_AF10_OTG_HS)
+#else
 #define USB_GPIO_AF (GPIO_AF10_OTG_FS)
 #endif
+#endif
 
 // USB pin low level, early peripheral initialization
 // PA12: D+, PA11: D-
 void usbdrv_gpio_init() {
     // turn GPIO-s into AF mode
     __HAL_RCC_GPIOA_CLK_ENABLE(); // turn ON GPIOA clocks
+#ifdef USB_HIGH_SPEED
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+#endif
 
     GPIO_InitTypeDef gpio_init;
     gpio_init.Mode = GPIO_MODE_AF_PP;
@@ -60,6 +68,19 @@ void usbdrv_gpio_init() {
     gpio_init.Pull = GPIO_NOPULL;
     gpio_init.Alternate = USB_GPIO_AF;
 
+#ifdef USB_HIGH_SPEED
+    gpio_init.Pin = GPIO_PIN_3 | GPIO_PIN_5; // D0, CK
+    HAL_GPIO_Init(GPIOA, &gpio_init);
+
+    // D1, D2, D7, D3, D4, D5, D6
+    gpio_init.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_5 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13;
+    HAL_GPIO_Init(GPIOB, &gpio_init);
+
+    // STP, DIR, NXT
+    gpio_init.Pin = GPIO_PIN_0 | GPIO_PIN_2 | GPIO_PIN_3;
+    HAL_GPIO_Init(GPIOC, &gpio_init);
+#else
+
     /* Pin initializations cannot be OR-ed together! */
 
     gpio_init.Pin = GPIO_PIN_11;
@@ -81,13 +102,20 @@ void usbdrv_gpio_init() {
     // gpio_init.Alternate = 0;
 
     // HAL_GPIO_Init(GPIOA, &gpio_init); // USB VBUSSENSE
+#endif
 }
 
 // ---------------
 
+#ifdef USB_HIGH_SPEED
+#define USB_IRQn OTG_HS_IRQn
+#else
+#define USB_IRQn OTG_FS_IRQn
+#endif
+
 // initialize USB subsystem
 void usbdrv_init() {
-    NVIC_DisableIRQ(OTG_FS_IRQn);
+    NVIC_DisableIRQ(USB_IRQn);
 
     usbdrv_init_global_state();
     usbdrv_gpio_init();
@@ -95,8 +123,8 @@ void usbdrv_init() {
     usbdrv_initial_ep0_setup();
     usbdrv_power_and_connect(true);
 
-    NVIC_SetPriority(OTG_FS_IRQn, 6);
-    NVIC_EnableIRQ(OTG_FS_IRQn);
+    NVIC_SetPriority(USB_IRQn, 0);
+    NVIC_EnableIRQ(USB_IRQn);
 }
 
 void usbdrv_reset() {
@@ -132,17 +160,30 @@ void usbdrv_init_global_state() {
 #endif
 }
 
-#if defined(USB_STM32H7)
+#ifdef USB_HIGH_SPEED
+__weak void usbdrv_ulpi_init() {
+    return;
+}
+#endif
+
+#if defined(USB_STM32H7) /*|| defined(USB_HIGH_SPEED)*/
 #define TOCAL_VALUE (0x00)
 #define TRDT_VALUE (0x05)
 #elif defined(USB_STM32F4)
+#if !defined(USB_HIGH_SPEED)
 #define TOCAL_VALUE (0x07)
 #define TRDT_VALUE (0x06)
+#else
+#define TOCAL_VALUE (0x07)
+#define TRDT_VALUE (0x09)
+#endif
 #endif
 
 // ---------------
 
 #define USB_LINESPEED_FULL_SPEED (0b11)
+#define USB_LINESPEED_FULL_SPEED_ULPI (0b01)
+#define USB_LINESPEED_HIGH_SPEED_ULPI (0b00)
 
 // initialize USB peripheral
 void usbdrv_periph_init() {
@@ -151,9 +192,17 @@ void usbdrv_periph_init() {
     WAIT_FOR_nBIT(PWR->CR3, PWR_CR3_USB33RDY);
 #endif
 
-    __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); // enable clock on USB peripheral
+#ifdef USB_STM32F4
 
-    HAL_Delay(1000);
+#ifdef USB_HIGH_SPEED
+    __HAL_RCC_USB_OTG_HS_CLK_ENABLE();      // enable HS USB peripheral
+    __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); // also enable ULPI module clock
+#else
+    __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); // enable FS USB peripheral
+#endif
+#endif
+
+    // HAL_Delay(1000);
 
     //__HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE();
     //__HAL_RCC_USB_OTG_FS_FORCE_RESET();
@@ -164,6 +213,23 @@ void usbdrv_periph_init() {
 
     SET_BIT(USBG->GRSTCTL, USB_OTG_GRSTCTL_CSRST); // reset USB core
     WAIT_FOR_BIT(USBG->GRSTCTL, USB_OTG_GRSTCTL_CSRST);
+#else
+
+#if defined(USB_HIGH_SPEED)
+    CLEAR_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_PHYSEL); // select the external HS PHY
+    CLEAR_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_TSDPS);
+    CLEAR_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_ULPIFSLS);
+
+    CLEAR_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_ULPIEVBUSD);
+    CLEAR_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_ULPIEVBUSI);
+    // SET_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_PHYSEL);
+
+    SET_BIT(USBG->GRSTCTL, USB_OTG_GRSTCTL_CSRST); // reset USB core
+    WAIT_FOR_BIT(USBG->GRSTCTL, USB_OTG_GRSTCTL_CSRST);
+
+    usbdrv_ulpi_init(); // initialize PHY
+#endif
+
 #endif
 
     CLEAR_BIT(USBG->GCCFG, USB_OTG_GCCFG_PWRDWN); // power down the peripheral
@@ -171,21 +237,32 @@ void usbdrv_periph_init() {
     CLEAR_BIT(USBG->GAHBCFG, USB_OTG_GAHBCFG_GINT);                            // mask all interrupts for now
     CLEAR_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_HNPCAP | USB_OTG_GUSBCFG_SRPCAP); // disable HNP and SRP
     WRITE_FIELD(USBG->GUSBCFG, USB_OTG_GUSBCFG_TRDT, TRDT_VALUE);              // set TRDT according to the RM
-    WRITE_FIELD(USBG->GUSBCFG, USB_OTG_GUSBCFG_TOCAL, TOCAL_VALUE);            // set TOCAL
-    SET_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_FDMOD);                             // force Device mode
+    // WRITE_FIELD(USBG->GUSBCFG, USB_OTG_GUSBCFG_TOCAL, TOCAL_VALUE);            // set TOCAL
+    CLEAR_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_FHMOD); // clear Host mode forcing
+    SET_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_FDMOD);   // force Device mode
+
+    HAL_Delay(25); // wait for Device mode forcing propagation
+    WAIT_FOR_BIT(USBG->GINTSTS, 0b1);
+
+    // SET_BIT(USBD->DCTL, USB_OTG_DCTL_SDIS); // soft disconnect peripheral (should be upper, but since it's controlled by a Device register, cannot be set before switching to device mode)
 
 #if defined(USB_STM32H7)
     CLEAR_BIT(USBG->GCCFG, USB_OTG_GCCFG_VBDEN);                                // turn on VBUSSENSE
     SET_BIT(USBG->GOTGCTL, USB_OTG_GOTGCTL_BVALOEN | USB_OTG_GOTGCTL_BVALOVAL); // force B-session
 #elif defined(USB_STM32F4)
     SET_BIT(USBG->GCCFG, USB_OTG_GCCFG_NOVBUSSENS); // turn off VBUSSENSE
+    CLEAR_BIT(USBG->GCCFG, USB_OTG_GCCFG_VBUSBSEN | USB_OTG_GCCFG_VBUSASEN);
 #endif
 
-
     // HAL_Delay(50); // it takes time to forcing Device mode takes effect
 
-    SET_BIT(USBD->DCTL, USB_OTG_DCTL_SDIS);                               // soft disconnect peripheral (should be upper, but since it's controlled by a Device register, cannot be set before switching to device mode)
+#ifdef USB_HIGH_SPEED
+    // WRITE_FIELD(USBD->DCFG, USB_OTG_DCFG_DSPD, USB_LINESPEED_FULL_SPEED);
+    // WRITE_FIELD(USBD->DCFG, USB_OTG_DCFG_DSPD, USB_LINESPEED_HIGH_SPEED_ULPI);
+    WRITE_FIELD(USBD->DCFG, USB_OTG_DCFG_DSPD, USB_LINESPEED_FULL_SPEED_ULPI);
+#else
     WRITE_FIELD(USBD->DCFG, USB_OTG_DCFG_DSPD, USB_LINESPEED_FULL_SPEED); // there's no other possible option
+#endif
 
     // allow specific interrupts
     uint32_t intmask =             /*USB_OTG_GINTMSK_WUIM |     // Wake up */
@@ -305,9 +382,9 @@ void usbdrv_fetch_endpoint_configuration(uint8_t config_index) {
 #define USB_RX_FIFO_SETUP_RESERVATION_DWORDS (10)
 #define USB_MIN_GROSS_TX_FIFO_SIZE (2 * USB_MIN_EP_FIFO_SIZE)
 
-#if defined(USB_STM32F4)
+#if defined(USB_STM32F4) && !defined(USB_HIGH_SPEED)
 #define USB_MIN_GROSS_RX_FIFO_SIZE (2 * USB_MIN_EP_FIFO_SIZE + USB_RX_FIFO_SETUP_RESERVATION_DWORDS * 4)
-#elif defined(USB_STM32H7)
+#elif defined(USB_STM32H7) || defined(USB_HIGH_SPEED)
 #define USB_MIN_GROSS_RX_FIFO_SIZE (256)
 #endif
 
@@ -382,10 +459,10 @@ void usbdrv_initial_ep0_setup() {
 
 // addresses of specific DIEPTXF registers, addresses from the RM
 static uint32_t *USB_pDIEPTXF[4] = {
-    (uint32_t *)(USBG + 0x028), // DIEPTXF0
-    (uint32_t *)(USBG + 0x104), // DIEPTXF1
-    (uint32_t *)(USBG + 0x108), // DIEPTXF2
-    (uint32_t *)(USBG + 0x10C), // DIEPTXF3
+    (uint32_t *)(((uint32_t)USBG) + 0x028), // DIEPTXF0
+    (uint32_t *)(((uint32_t)USBG) + 0x104), // DIEPTXF1
+    (uint32_t *)(((uint32_t)USBG) + 0x108), // DIEPTXF2
+    (uint32_t *)(((uint32_t)USBG) + 0x10C), // DIEPTXF3
     // TODO: HS USB controller has more endpoints
 };
 
@@ -423,15 +500,16 @@ void usbdrv_configure_endpoint(uint8_t ep, uint8_t dir, const USBDRV_EpConfig *c
         } else {
             WRITE_FIELD(USBINEP[ep].DIEPCTL, USB_OTG_DIEPCTL_EPTYP, cfg->type);            // program endpoint type
             WRITE_FIELD(USBINEP[ep].DIEPCTL, USB_OTG_DIEPCTL_MPSIZ, cfg->max_packet_size); // program maximum packet size
-            SET_BIT(USBINEP[ep].DIEPCTL, USB_OTG_DIEPCTL_USBAEP);                          // the endpoint is active in the current configuration
+	    SET_BIT(USBINEP[ep].DIEPCTL, USB_OTG_DIEPCTL_USBAEP);                          // the endpoint is active in the current configuration
         }
 
+
         // ---- common for all endpoints ----
 
         // program FIFO corresponding FIFO number
         WRITE_FIELD(USBINEP[ep].DIEPCTL, USB_OTG_DIEPCTL_TXFNUM, ep);
 
-        // store Tx FIFO size (both fields are WORD units, NOT bytes, this RM is missing this information!)
+        // store Tx FIFO size (both fields are WORD units, NOT bytes, RM is missing this information!)
         uint32_t tx_fifo_config = ((cfg->fifo_size >> 2) << USB_OTG_DIEPTXF_INEPTXFD_Pos) | (cfg->fifo_address >> 2); // combine size in DWORDs and address
         *(USB_pDIEPTXF[ep]) = tx_fifo_config;                                                                         // save
 
@@ -601,7 +679,7 @@ uint32_t usbdrv_arm_IN_endpoint(uint8_t ep, const uint8_t *data, uint16_t len) {
         SET_BIT(USBINEP[ep].DIEPCTL, USB_OTG_DIEPCTL_EPENA | USB_OTG_DIEPCTL_CNAK);
     }
 
-    // turn interrupt generation on only, if this is NOT the last FIFO write considering the current transfer
+    // turn on interrupt generation only, if this is NOT the last FIFO write considering the current transfer
     if (len > writeSize) {
         USBD->DIEPEMPMSK |= ((uint32_t)(1 << ep));
     }
@@ -609,6 +687,8 @@ uint32_t usbdrv_arm_IN_endpoint(uint8_t ep, const uint8_t *data, uint16_t len) {
     // disable ALL USB interrupts to prevent access to specific registers (see errata)
     CLEAR_BIT(USBG->GAHBCFG, USB_OTG_GAHBCFG_GINT);
 
+    // WAIT_FOR_nBIT(USBINEP[ep].DIEPINT, USB_OTG_DIEPINT_TXFE);
+
     // https://github.com/iliasam/STM32F4_USB_MICROPHONE/blob/master/Libraries/STM32_USB_OTG_Driver/src/usb_dcd_int.c#L655
     // https://github.com/iliasam/STM32F4_USB_MICROPHONE/blob/master/Libraries/STM32_USB_OTG_Driver/src/usb_core.c#L168
 
@@ -888,7 +968,12 @@ bool usbdrv_get_endpoint_interrupt_flag(uint8_t ep, uint8_t dir) {
 #define PROCESS_EVENT(evt, data) usbdrv_process_event((evt), (data))
 #endif
 
-void OTG_FS_IRQHandler() {
+#ifdef USB_HIGH_SPEED
+void OTG_HS_IRQHandler()
+#else
+void OTG_FS_IRQHandler()
+#endif
+{
 
     uint32_t ints = USBG->GINTSTS;
 
@@ -949,4 +1034,4 @@ void OTG_FS_IRQHandler() {
     }
 
     return;
-}
\ No newline at end of file
+}