From 6edf06c2cac4b469f8efd71d02c1c2632e2d6cd4 Mon Sep 17 00:00:00 2001
From: Epagris <wabe@t-email.hu>
Date: Tue, 29 Oct 2024 16:43:18 +0100
Subject: [PATCH] - polling with delay added - H7xx initialization code
 corrected

---
 usb_common.h |  2 ++
 usb_driver.c | 30 ++++++++++++++++++++----------
 2 files changed, 22 insertions(+), 10 deletions(-)

diff --git a/usb_common.h b/usb_common.h
index da817c0..63c9b9e 100644
--- a/usb_common.h
+++ b/usb_common.h
@@ -8,7 +8,9 @@
 #define READ_FIELD(r,f) (((r) & (f##_Msk)) >> (f##_Pos))
 #define WRITE_FIELD(r,f,v) ((r) = ((r) & ~(f##_Msk)) | (v << (f##_Pos)))
 #define WAIT_FOR_BIT(r,b) while ((r) & (b)) {}
+#define WAIT_FOR_BIT_DELAY(r,b,d) while ((r) & (b)) { HAL_Delay((d)); }
 #define WAIT_FOR_nBIT(r,b) while (!((r) & (b))) {}
+#define WAIT_FOR_nBIT_DELAY(r,b,d) while (!((r) & (b))) { HAL_Delay((d)); }
 
 #define DWORD_ALIGN __attribute__((aligned(4)))
 
diff --git a/usb_driver.c b/usb_driver.c
index 0327a51..3783047 100644
--- a/usb_driver.c
+++ b/usb_driver.c
@@ -3,8 +3,11 @@
 
 #include <memory.h>
 
+#include "flatUSB/usb_common_defs.h"
+#include "stm32h743xx.h"
 #include "usb_common.h"
-#include "usb_core_types.h"
+
+#include <stm32h7xx_hal.h>
 
 #include "desc/usb_desc.h"
 
@@ -55,7 +58,7 @@ static const char *FIFO_STATUS_STR[6] = {
 #ifndef STM32H723xx
 #define USB_GPIO_AF (GPIO_AF10_OTG2_FS)
 #else
-//#define USB_GPIO_AF (GPIO_AF10_OTG1_HS)
+// #define USB_GPIO_AF (GPIO_AF10_OTG1_HS)
 #endif
 #elif defined(USB_STM32F4)
 #ifdef USB_HIGH_SPEED
@@ -182,7 +185,6 @@ void usbdrv_init_global_state() {
 
 // ---------------
 
-
 #ifdef USB_HIGH_SPEED
 __weak void usbdrv_ulpi_init() {
     return;
@@ -211,10 +213,15 @@ __weak void usbdrv_ulpi_init() {
 // initialize USB peripheral
 void usbdrv_periph_init() {
 #if defined(USB_STM32H7)
+    // THIS SHOULD NOT BE TOUCHED!
     HAL_PWREx_EnableUSBVoltageDetector();
-    //WAIT_FOR_nBIT(PWR->CR3, PWR_CR3_USB33RDY);
+    WAIT_FOR_nBIT_DELAY(PWR->CR3, PWR_CR3_USB33RDY, 1);
 
+#if defined(STM32H723xx) // only a single USB HS peripheral is present on STM32H723 devices
     __HAL_RCC_USB1_OTG_HS_CLK_ENABLE();
+#else
+    __HAL_RCC_USB2_OTG_FS_CLK_ENABLE();
+#endif
 #endif
 
 #ifdef USB_STM32F4
@@ -227,7 +234,7 @@ void usbdrv_periph_init() {
 #endif
 #endif
 
-    HAL_Delay(1000);
+    //HAL_Delay(1000);
 
     //__HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE();
     //__HAL_RCC_USB_OTG_FS_FORCE_RESET();
@@ -236,9 +243,11 @@ void usbdrv_periph_init() {
 #if defined(USB_STM32H7)
     SET_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_PHYSEL); // select the internal FS PHY
 
-    SET_BIT(USBG->GRSTCTL, USB_OTG_GRSTCTL_CSRST); // reset USB core
+    WAIT_FOR_nBIT_DELAY(USBG->GRSTCTL, USB_OTG_GRSTCTL_AHBIDL, 1);
+
+    SET_BIT(USBG->GRSTCTL, USB_OTG_GRSTCTL_CSRST); // reset the USB core
     HAL_Delay(1);
-    WAIT_FOR_BIT(USBG->GRSTCTL, USB_OTG_GRSTCTL_CSRST);
+    WAIT_FOR_BIT_DELAY(USBG->GRSTCTL, USB_OTG_GRSTCTL_CSRST, 1);
 #else
 
 #if defined(USB_HIGH_SPEED)
@@ -251,13 +260,14 @@ void usbdrv_periph_init() {
     // SET_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_PHYSEL);
 
     SET_BIT(USBG->GRSTCTL, USB_OTG_GRSTCTL_CSRST); // reset USB core
+    HAL_Delay(1);
     WAIT_FOR_BIT(USBG->GRSTCTL, USB_OTG_GRSTCTL_CSRST);
 
     usbdrv_ulpi_init(); // initialize PHY
 #endif
 
 #endif
-    CLEAR_BIT(USBG->GCCFG, USB_OTG_GCCFG_PWRDWN); // power down the peripheral
+    CLEAR_BIT(USBG->GCCFG, USB_OTG_GCCFG_PWRDWN); // power the internal transceiver peripheral
 
     CLEAR_BIT(USBG->GAHBCFG, USB_OTG_GAHBCFG_GINT);                            // mask all interrupts for now
     CLEAR_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_HNPCAP | USB_OTG_GUSBCFG_SRPCAP); // disable HNP and SRP
@@ -272,7 +282,7 @@ void usbdrv_periph_init() {
     // SET_BIT(USBD->DCTL, USB_OTG_DCTL_SDIS); // soft disconnect peripheral (should be upper, but since it's controlled by a Device register, cannot be set before switching to device mode)
 
 #if defined(USB_STM32H7)
-    CLEAR_BIT(USBG->GCCFG, USB_OTG_GCCFG_VBDEN);                                // turn on VBUSSENSE
+    CLEAR_BIT(USBG->GCCFG, USB_OTG_GCCFG_VBDEN);                                // turn off VBUSSENSE
     SET_BIT(USBG->GOTGCTL, USB_OTG_GOTGCTL_BVALOEN | USB_OTG_GOTGCTL_BVALOVAL); // force B-session
 #elif defined(USB_STM32F4)
     SET_BIT(USBG->GCCFG, USB_OTG_GCCFG_NOVBUSSENS); // turn off VBUSSENSE
@@ -476,7 +486,7 @@ void usbdrv_build_fifo() {
     }
 }
 
-const char * usbdrv_get_fifo_addr_table() {
+const char *usbdrv_get_fifo_addr_table() {
     return usbdrv_addr_table;
 }