- converted to CMake-managed library
- added CMake-managed conditional compilation of desired USB classes - STM32F407xx and STM32H743/5xx support joined in the driver files
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f6e3d48476
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@ -1,13 +1,30 @@
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target_sources(
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${CMAKE_PROJECT_NAME}
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PUBLIC
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cmake_minimum_required(VERSION 3.15)
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set(FLATUSB_TARGET flatUSB)
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if (NOT FLATUSB_TARGET_TAG STREQUAL "")
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set(${FLATUSB_TARGET} "${FLATUSB_TARGET}_${FLATUSB_TARGET_TAG}")
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endif()
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set(FLATUSB_CLASSES_SRC "")
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if ("CDC_ACM" IN_LIST FLATUSB_CLASSES)
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list(APPEND FLATUSB_CLASSES_SRC
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class/cdc.c
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class/cdc.h
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)
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endif()
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if ("CDC_EEM" IN_LIST FLATUSB_CLASSES)
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list(APPEND FLATUSB_CLASSES_SRC
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class/eem.c
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class/eem.h
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)
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endif()
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CMakeLists.txt
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message("flatUSB classes selected: ${FLATUSB_CLASSES}")
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set(FLATUSB_SRC
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${FLATUSB_CLASSES_SRC}
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desc/usb_desc.c
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desc/usb_desc.h
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@ -25,3 +42,8 @@ target_sources(
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# utils/gen_queue.c
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# utils/gen_queue.h
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)
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add_library(${FLATUSB_TARGET} STATIC ${FLATUSB_SRC})
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target_include_directories(${FLATUSB_TARGET} PRIVATE ${FLATUSB_INCLUDES})
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target_compile_options(${FLATUSB_TARGET} PRIVATE ${FLATUSB_CPU_PARAMS})
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target_compile_definitions(${FLATUSB_TARGET} PRIVATE ${FLATUSB_COMPILE_DEFS})
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@ -1,8 +1,13 @@
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#ifndef CORE_USB_USB_COMMON_DEFS
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#define CORE_USB_USB_COMMON_DEFS
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#if defined(STM32H745xx) || defined(STM32H743xx)
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#include <stm32h7xx.h>
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#include <stm32h7xx_hal.h>
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#elif defined(STM32F407xx)
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#include <stm32f407xx.h>
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#include <stm32f4xx_hal.h>
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#endif
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#define USBG (USB_OTG_FS)
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#define USBD ((USB_OTG_DeviceTypeDef *) ((uint32_t)(USBG) + (uint32_t)(USB_OTG_DEVICE_BASE)))
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74
usb_driver.c
74
usb_driver.c
@ -42,6 +42,12 @@ static const char *FIFO_STATUS_STR[6] = {
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// ---------------
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#if defined(STM32H745xx) || defined(STM32H743xx)
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#define USB_GPIO_AF (GPIO_AF10_OTG1_FS)
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#elif defined(STM32F407xx)
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#define USB_GPIO_AF (GPIO_AF10_OTG_FS)
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#endif
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// USB pin low level, early peripheral initialization
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// PA12: D+, PA11: D-
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void usbdrv_gpio_init() {
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@ -50,18 +56,18 @@ void usbdrv_gpio_init() {
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GPIO_InitTypeDef gpio_init;
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gpio_init.Mode = GPIO_MODE_AF_PP;
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gpio_init.Pin = GPIO_PIN_12;
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gpio_init.Pin = GPIO_PIN_11 | GPIO_PIN_12;
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gpio_init.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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gpio_init.Pull = GPIO_NOPULL;
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gpio_init.Alternate = GPIO_AF10_OTG_FS;
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gpio_init.Alternate = USB_GPIO_AF;
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HAL_GPIO_Init(GPIOA, &gpio_init); // USB D+
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// HAL_GPIO_WritePin(GPIOA, GPIO_PIN_11, GPIO_PIN_SET);
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gpio_init.Pin = GPIO_PIN_11;
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gpio_init.Pull = GPIO_NOPULL;
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HAL_GPIO_Init(GPIOA, &gpio_init); // USB D-
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// gpio_init.Pin = GPIO_PIN_11;
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// gpio_init.Pull = GPIO_NOPULL;
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// HAL_GPIO_Init(GPIOA, &gpio_init); // USB D-
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// gpio_init.Mode = GPIO_MODE_INPUT;
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// gpio_init.Pin = GPIO_PIN_9;
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@ -128,9 +134,20 @@ void usbdrv_init_global_state() {
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// initialize USB peripheral
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void usbdrv_periph_init() {
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__HAL_RCC_USB_OTG_FS_CLK_ENABLE(); // enable clock on USB peripheral
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//__HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE();
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//__HAL_RCC_USB_OTG_FS_FORCE_RESET();
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//__HAL_RCC_USB_OTG_FS_RELEASE_RESET();
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// HAL_PWREx_EnableUSBReg();
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// HAL_PWREx_EnableUSBVoltageDetector();
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#if defined(STM32H745xx) || defined(STM32H743xx)
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SET_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_PHYSEL); // select the internal FS PHY
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SET_BIT(USBG->GRSTCTL, USB_OTG_GRSTCTL_CSRST); // reset USB core
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WAIT_FOR_BIT(USBG->GRSTCTL, USB_OTG_GRSTCTL_CSRST);
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#endif
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CLEAR_BIT(USBG->GCCFG, USB_OTG_GCCFG_PWRDWN); // power down the peripheral
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CLEAR_BIT(USBG->GAHBCFG, USB_OTG_GAHBCFG_GINT); // mask all interrupts for now
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@ -138,7 +155,13 @@ void usbdrv_periph_init() {
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WRITE_FIELD(USBG->GUSBCFG, USB_OTG_GUSBCFG_TRDT, 0x06); // set TRDT according to the RM
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WRITE_FIELD(USBG->GUSBCFG, USB_OTG_GUSBCFG_TOCAL, 0x07); // set TOCAL
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SET_BIT(USBG->GUSBCFG, USB_OTG_GUSBCFG_FDMOD); // force Device mode
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#if defined(STM32H745xx) || defined(STM32H743xx)
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CLEAR_BIT(USBG->GCCFG, USB_OTG_GCCFG_VBDEN); // turn off VBUSSENSE
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SET_BIT(USBG->GOTGCTL, USB_OTG_GOTGCTL_BVALOEN | USB_OTG_GOTGCTL_BVALOVAL); // force B-session
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#elif defined(STM32F407xx)
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SET_BIT(USBG->GCCFG, USB_OTG_GCCFG_NOVBUSSENS); // turn off VBUSSENSE
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#endif
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// HAL_Delay(50); // it takes time to forcing Device mode takes effect
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@ -262,18 +285,43 @@ void usbdrv_fetch_endpoint_configuration(uint8_t config_index) {
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#define USB_FIFO_MARGIN (8)
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#define USB_RX_FIFO_SETUP_RESERVATION_DWORDS (10)
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#define USB_MIN_GROSS_TX_FIFO_SIZE (2 * USB_MIN_EP_FIFO_SIZE)
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#ifdef STM32F407xx
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#define USB_MIN_GROSS_RX_FIFO_SIZE (2 * USB_MIN_EP_FIFO_SIZE + USB_RX_FIFO_SETUP_RESERVATION_DWORDS * 4)
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#elif defined(STM32H745xx) || defined(STM32H743xx)
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#define USB_MIN_GROSS_RX_FIFO_SIZE (256)
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#endif
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// build FIFO (compute addresses)
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void usbdrv_build_fifo() {
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// ---- OUT ----
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uint16_t fifo_size = USB_MIN_GROSS_RX_FIFO_SIZE; // at least this large
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uint16_t next_fifo_addr = 0x00; // Rx FIFO begins at address zero
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for (uint8_t i = 0; i < USB_NUM_OF_ENDPOINTS; i++) { // look for greatest FIFO size
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if (gs.ep_OUT[i].is_configured) {
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fifo_size = CEIL4(MAX(fifo_size, gs.ep_OUT[i].max_packet_size)); // compare and replace if necessary
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uint16_t largest_packet_size = 0; // largest packet size
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uint16_t control_ep_count = 0; // number of control endpoints
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uint16_t out_ep_count = 0; // count of OUT pipes
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for (uint8_t i = 0; i < USB_NUM_OF_ENDPOINTS; i++) { // gather config information
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// look for largest packet size
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if (gs.ep_OUT[i].is_configured) { // examine OUT EPs
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largest_packet_size = MAX(largest_packet_size, gs.ep_OUT[i].max_packet_size);
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out_ep_count++;
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}
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if (gs.ep_IN[i].is_configured) { // examine IN EPs
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largest_packet_size = MAX(largest_packet_size, gs.ep_IN[i].max_packet_size);
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}
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// count control endpoints
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if (((gs.ep_OUT[i].is_configured) && (gs.ep_OUT[i].type == UT_Control)) ||
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((gs.ep_IN[i].is_configured) && (gs.ep_IN[i].type == UT_Control))) {
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control_ep_count++;
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}
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}
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// RX FIFO size calculation expression from the RM
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uint16_t fifo_size_dwords = (5 * control_ep_count + 8) + (CEILDIV4(largest_packet_size) + 1) + (2 * out_ep_count) + 1; // calculate RX FIFO size in DWORDS
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uint16_t fifo_size = fifo_size_dwords * 4; // calculate RX FIFO size in bytes
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fifo_size = CEIL4(MAX(fifo_size, USB_MIN_GROSS_RX_FIFO_SIZE)); // RX FIFO should be at least this large
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//fifo_size *= 2; // TODO:
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gs.rx_fifo_size = fifo_size; // save Rx FIFO size for later
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next_fifo_addr += fifo_size; // advance next FIFO address
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usbdrv_set_rx_fifo_size(fifo_size); // set Rx FIFO size in hardware
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@ -573,7 +621,7 @@ uint32_t usbdrv_arm_IN_endpoint(uint8_t ep, const uint8_t *data, uint16_t len) {
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// arm OUT endpoint
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uint32_t usbdrv_arm_OUT_endpoint(uint8_t ep, uint8_t size) {
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// arm endpoint only if it was not armed before
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// arm endpoint only if it was not armed before OR if it's the EP0 OUT which is always enabled, but responds NAK after a successful transfer
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if (READ_BIT(USBOUTEP[ep].DOEPCTL, USB_OTG_DOEPCTL_EPENA)) {
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return 0;
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}
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@ -582,7 +630,11 @@ uint32_t usbdrv_arm_OUT_endpoint(uint8_t ep, uint8_t size) {
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size = MIN(gs.ep_OUT[ep].max_packet_size, size);
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// write registers
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USBOUTEP[ep].DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT | size; // program DIEPTSIZ with maximum (expected) transfer length and set PCKTCNT to make ready for reception
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uint32_t doeptsiz = USBOUTEP[ep].DOEPTSIZ;
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doeptsiz &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); // clear XFERSIZ bits
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doeptsiz |= USB_OTG_DOEPTSIZ_PKTCNT | size; // program DIEPTSIZ with maximum (expected) transfer length and set PCKTCNT to make ready for reception
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USBOUTEP[ep].DOEPTSIZ = doeptsiz; // write value to the actual register
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SET_BIT(USBOUTEP[ep].DOEPCTL, USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK); // enable endpoint and clear NAK
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// return with armed size
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