`timescale 1ns / 1ps

module cdc (
	input tclk, // target domain's clock
	input rst,
	
	input sin, // input data from the source domain
	output tout // output data to the target domain
);

reg [1:0] pipe;
always @(posedge tclk)
begin
	if (rst)
	begin
		pipe <= 0;
	end
	else
	begin
		pipe[0] <= sin;
		pipe[1] <= pipe[0];
	end
end

assign tout = pipe[1];

endmodule