// billentyű-felismerő
module key_matcher(
	input wire clk, // órajel (1MHz)
	input wire rst, // szinkron reset

	input wire [7:0] scan_code, // billentyűkód
	input wire sc_valid, // a kimeneten érvényes adat van
	 
	output reg [6:0] key_states // a figyelt billentyűk állapotai
);

// ---------------

// billentyűkódok
localparam SC_A   = 8'h1C; // A
localparam SC_D   = 8'h23; // D
localparam SC_N4  = 8'h6B; // NumPad 4
localparam SC_N6  = 8'h74; // NumPad 6
localparam SC_N   = 8'h31; // N
localparam SC_M   = 8'h3A; // M
localparam SC_ESC = 8'h76; // Escape

localparam SC_REL = 8'hF0; // billentyű elengedése előtag

// -------------

// bejövő adat léptetőregisztere
reg [15:0] shr;
always @(posedge clk)
begin
	if (rst)
	begin
		shr <= 16'b0;
	end
	else if (sc_valid)
	begin
		shr <= { shr[7:0], scan_code };
	end
end

wire [7:0] b0 = shr[7:0];
wire [7:0] b1 = shr[15:8];

// billentyű-mintaillesztés
always @(posedge clk)
begin
	if (rst)
	begin
		key_states <= 6'b0;
	end
	else
	begin
		if ((b0 == SC_A) && (b1 != SC_REL)) // A lenyomva
		begin
			key_states[0] <= 1'b1;
		end
		else if ((b0 == SC_A) && (b1 == SC_REL)) // A felengedve
		begin
			key_states[0] <= 1'b0;
		end
		
		else if ((b0 == SC_D) && (b1 != SC_REL))
		begin
			key_states[1] <= 1'b1;
		end
		else if ((b0 == SC_D) && (b1 == SC_REL))
		begin
			key_states[1] <= 1'b0;
		end
		
		else if ((b0 == SC_N4) && (b1 != SC_REL))
		begin
			key_states[2] <= 1'b1;
		end
		else if ((b0 == SC_N4) && (b1 == SC_REL))
		begin
			key_states[2] <= 1'b0;
		end
		
		else if ((b0 == SC_N6) && (b1 != SC_REL))
		begin
			key_states[3] <= 1'b1;
		end
		else if ((b0 == SC_N6) && (b1 == SC_REL))
		begin
			key_states[3] <= 1'b0;
		end
		
		else if ((b0 == SC_N) && (b1 != SC_REL))
		begin
			key_states[4] <= 1'b1;
		end
		else if ((b0 == SC_N) && (b1 == SC_REL))
		begin
			key_states[4] <= 1'b0;
		end
		
		else if ((b0 == SC_M) && (b1 != SC_REL))
		begin
			key_states[5] <= 1'b1;
		end
		else if ((b0 == SC_M) && (b1 == SC_REL))
		begin
			key_states[5] <= 1'b0;
		end
		
		else if ((b0 == SC_ESC) && (b1 != SC_REL))
		begin
			key_states[6] <= 1'b1;
		end
		else if ((b0 == SC_ESC) && (b1 == SC_REL))
		begin
			key_states[6] <= 1'b0;
		end
	end
end

endmodule