module pp_top(
	input wire clk,
	input wire rst_n,
	
	output wire [4:0] vga_sigs,
	
	output wire [3:0] leds_n,
	input wire [3:0] btns_n,
	output wire [7:0] segs_n,
	output wire [3:0] digs_n,
	input wire ps2_ck,
	input wire ps2_dat,
	output wire beep_n
);

// bemenetek-kimenetek ponált-negált átalakítása
wire rst = ~rst_n;
wire [3:0] btns = ~btns_n;
assign leds_n = ~leds;

// 65MHz és 1MHz órajelgenerátor
wire clk65M;
wire clk1M;
wire locked;

reg srst;

clk_gen main_clk_gen(
	.areset(rst),
	.inclk0(clk),
	.c0(clk65M),
	.c1(clk1M),
	.locked(locked)
);

// -----------

wire [7:0] data;
wire valid;
ps2_host ps2(
	.clk(clk1M),
	.rst(srst),
	
	.ps2_ck(ps2_ck),
	.ps2_dat(ps2_dat),
	
	.data(data),
	.valid(valid),
	.ack(1'b1)
);

//always @(posedge clk1M)
//begin
//	if (rst)
//	begin
//		d <= 16'b0;
//	end
//	else if (valid)
//	begin 
//		d <= { d[7:0], data };
//	end
//end

// -----------

wire [6:0] ks;
key_matcher km(
	.clk(clk1M),
	.rst(rst),
	
	.scan_code(data),
	.sc_valid(valid),
	.key_states(ks)
);

// -----------

// Játéklogika
wire [9:0] ballx;
wire [9:0] bally;
wire [9:0] pod1x;
wire [9:0] pod2x;
wire [7:0] score1;
wire [7:0] score2;
wire hit;
wire miss;

game_controller game (
	.clk(clk1M),
	.rst(srst),
	
	.start(ks[4]),
	.acknowledge(ks[5]),
	
	.pod1x(pod1x),
	.pod2x(pod2x),
	.ballx(ballx),
	.bally(bally),
	
	.move_pod1_en(ks[0] ^ ks[1]),
	.move_pod1_dir(ks[1]),
	.move_pod2_en(ks[2] ^ ks[3]),
	.move_pod2_dir(ks[3]),
	
	.score1(score1),
	.score2(score2),
	.clear_score(ks[6]),
	
	.hit(hit),
	.miss(miss)
);

wire beep;
assign beep_n = ~beep;

beep beeper(
	.clk(clk1M),
	.rst(srst),
	
	.hit(hit),
	.miss(miss),
	.beep(beep)
);

// VGA renderer
wire hsync;
wire vsync;
wire [2:0] rgb;
vga /* #(
	.COLS(800),
	.ROWS(600),
	.H_FRONT_PORCH(40),
	.H_SYNC_PULSE(128),
	.H_BACK_PORCH(88),
	.V_FRONT_PORCH(1),
	.V_SYNC_PULSE(4),
	.V_BACK_PORCH(23),
	.H_SYNC_NEG(0),
	.V_SYNC_NEG(0) 
) */ vga (
	.pclk(clk65M),
	.sclk(clk1M),
	.rst(srst),
	
	.hsync(hsync),
	.vsync(vsync),
	.rgb(rgb),
	
	.pod1x(pod1x),
	.pod2x(pod2x),
	.ballx(ballx),
	.bally(bally)
);

assign vga_sigs = { hsync, vsync, rgb };

// -----------

wire [3:0] d0;
wire [3:0] d1;
wire [3:0] d2;
wire [3:0] d3;

assign { d3, d2, d1, d0 } = { score1, score2 };

//reg [15:0] d;
//assign { d3, d2, d1, d0 } = d;

sseg_disp disp(
	.clk(clk1M),
	.rst(srst),
	
	.d0(d0),
	.d1(d1),
	.d2(d2),
	.d3(d3),
	
	.dps(4'b0100),
	
	.segs_n(segs_n),
	.digs_n(digs_n)
);


// -----------

reg [19:0] cntr;
always @(posedge clk1M, posedge rst)
begin
	if (rst)
	begin
		cntr <= 0;
	end
	else
	begin
		cntr <= cntr + 1;
	end
end

wire tc = &cntr;

reg reset_issued;
always @(posedge clk1M, posedge rst)
begin
	if (rst)
	begin
		reset_issued <= 1'b0;
		srst <= 1'b0;
	end
	else if (tc && !reset_issued)
	begin
		srst <= 1'b1;
		reset_issued <= 1'b1;
	end
	else
	begin
		srst <= 1'b0;
	end
end

// -----------

//always @(posedge clk1M)
//begin
//	if (rst)
//	begin
//		ld0 <= 0;
//	end
//	else if (tc)
//	begin
//		ld0 <= ~ld0;
//	end
//end


wire [3:0] leds = ks[3:0];

endmodule