114 lines
1.5 KiB
Verilog
114 lines
1.5 KiB
Verilog
// PS/2 vezérlő
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module ps2_host (
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input wire clk, // órajel (1MHz)
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input wire rst, // szinkron reset
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input wire ps2_ck, // PS/2 órajel
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input wire ps2_dat, // PS/2 adat
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output reg [7:0] data, // adatbájt-kimenet
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output reg valid, // adat érvényes a kimeneten
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input wire ack // adat olvasva
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);
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// PS/2 órajel-felismerés
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reg prev_ps2_ck;
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always @(posedge clk)
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begin
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if (rst)
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begin
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prev_ps2_ck <= 1'b1;
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end
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else
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begin
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prev_ps2_ck <= ps2_ck;
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end
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end
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wire ck_fallen = !prev_ps2_ck && !ps2_ck;
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wire ck_risen = prev_ps2_ck && ps2_ck;
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reg ck_state, prev_ck_state;
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always @(posedge clk)
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begin
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if (rst)
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begin
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ck_state <= 1'b1;
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prev_ck_state <= 1'b1;
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end
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else
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begin
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if (ck_state && ck_fallen)
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begin
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ck_state <= 1'b0;
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end
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else if (!ck_state && ck_risen)
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begin
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ck_state <= 1'b1;
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end
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prev_ck_state <= ck_state;
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end
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end
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wire ck_falling = prev_ck_state && !ck_state;
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// bitszámláló
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reg [3:0] cntr;
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always @(posedge clk)
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begin
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if (rst)
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begin
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cntr <= 4'b0;
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end
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else if (ck_falling)
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begin
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cntr <= cntr + 4'b1;
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end
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else if (cntr == 4'd11)
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begin
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cntr <= 4'b0;
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end
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end
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// adat beléptetése
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reg [10:0] shr;
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always @(posedge clk)
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begin
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if (rst)
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begin
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shr <= 11'b0;
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end
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else if (ck_falling)
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begin
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shr <= { ps2_dat, shr[10:1] };
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end
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end
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// adat kiadása
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always @(posedge clk)
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begin
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if (rst)
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begin
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data <= 8'b0;
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valid <= 1'b0;
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end
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else
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begin
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if (valid && ack)
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begin
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valid <= 1'b0;
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end
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if (cntr == 4'd11)
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begin
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data <= shr[8:1];
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valid <= 1'b1;
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end
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end
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end
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endmodule
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