104 lines
1.4 KiB
Verilog
104 lines
1.4 KiB
Verilog
module beep #(
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parameter HIT_PERIOD = 1,
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parameter HIT_LEN = 150,
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parameter MISS_PERIOD = 3,
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parameter MISS_LEN = 1400,
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parameter HALF_MS_DIV = 500
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)(
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input wire clk,
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input wire rst,
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input wire hit,
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input wire miss,
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output reg beep
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);
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reg [8:0] cntr;
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always @(posedge clk)
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begin
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if (rst)
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begin
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cntr <= 9'd0;
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end
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else
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begin
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if (cntr != (HALF_MS_DIV - 1))
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begin
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cntr <= cntr + 9'd1;
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end
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else
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begin
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cntr <= 9'd0;
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end
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end
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end
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wire tc = (cntr == (HALF_MS_DIV - 1));
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reg [3:0] period;
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reg [3:0] subperiod_cntr;
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always @(posedge clk)
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begin
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if (rst || (!sound_playing))
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begin
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beep <= 1'b0;
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subperiod_cntr <= 4'd0;
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end
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else if (sound_playing && tc)
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begin
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if (subperiod_cntr != period)
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begin
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subperiod_cntr <= subperiod_cntr + 4'd1;
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end
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else
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begin
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subperiod_cntr <= 4'd0;
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beep <= ~beep;
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end
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end
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end
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reg sound_playing;
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reg [10:0] len;
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always @(posedge clk)
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begin
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if (rst)
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begin
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sound_playing <= 1'b0;
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len <= 11'd0;
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period <= 4'd0;
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end
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else if ((!sound_playing) && (hit || miss))
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begin
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if (hit)
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begin
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period <= HIT_PERIOD;
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len <= HIT_LEN;
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end
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else if (miss)
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begin
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period <= MISS_PERIOD;
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len <= MISS_LEN;
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end
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sound_playing <= 1'b1;
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end
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else if (sound_playing && tc)
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begin
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if (len != 10'd0)
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begin
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len <= len - 10'd1;
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end
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else
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begin
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sound_playing <= 1'b0;
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end
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end
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end
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endmodule
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