28 lines
366 B
Verilog
28 lines
366 B
Verilog
`timescale 1ns / 1ps
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module cdc (
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input tclk, // target domain's clock
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input rst,
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input sin, // input data from the source domain
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output tout // output data to the target domain
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);
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reg [1:0] pipe;
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always @(posedge tclk)
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begin
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if (rst)
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begin
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pipe <= 0;
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end
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else
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begin
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pipe[0] <= sin;
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pipe[1] <= pipe[0];
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end
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end
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assign tout = pipe[1];
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endmodule
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